Synchronous Semiconductor Power Reduction via Gate Control
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Solution Overview
Problem
Synchronous semiconductor devices face challenges in reducing power consumption when inactive, particularly due to high clock signal frequencies, as existing methods either stop the input buffer or internal clock signal, which are not suitable for high-frequency operations or fail to reduce charge/discharge currents effectively.
Innovation Solution
A synchronous semiconductor device design that includes input buffers, latch-signal generating circuits, latch circuits, delay circuits, and gate circuits arranged between input buffers and delay circuits, where the gate circuits inactivate internal signals in response to a chip select signal, allowing the input buffer and internal clock signal to remain operational while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the bias current of the differential amplifier circuit is cut to reduce power consumption, then power consumption is reduced, but a predetermined time is necessary to make the differential amplifier circuit operable again
Solution Approach 1:
The patent extracts the power consumption problem from the input buffer by introducing a separate control mechanism. The chip select signal controls the enable input of the input buffer independently from the clock signal, allowing the buffer to be disabled when not needed while maintaining clock signal continuity. This separates the power control function from the operational control function.
Solution Approach 2:
The patent applies preliminary action by keeping the input buffer in a ready state with continuous clock signaling, but disabling its functional output through the enable control. This allows the buffer to be immediately reactivated when the chip select signal changes, eliminating restoration delay while still achieving power savings during inactive periods.
2Use of energy by moving object
If the clock signal supply to the latch circuit is stopped to reduce power consumption, then power consumption is reduced, but the operation cannot be restarted immediately
Solution Approach 1:
The patent segments the control signals into separate functional components: the clock signal continues uninterrupted to maintain circuit readiness, while the enable signal (controlled by chip select) separately manages the functional activation of the input buffer. This segmentation allows independent optimization of power consumption and restart speed.
3Use of energy by moving object
If the operation of the latch circuit is stopped to reduce power consumption, then power consumption is reduced, but charge/discharge current from delay circuit cannot be reduced
Solution Approach 1:
The patent introduces an intermediary enable control signal that mediates between the continuous clock signal and the latch circuit operation. This enable signal, controlled by the chip select input, allows the clock to continue flowing through the delay circuit (maintaining readiness) while preventing functional operation of the latch, thereby reducing charge/discharge currents without sacrificing restart capability.
Data Source
AI summary
A semiconductor device includes first, second and third terminals respectively receiving first, second and third input signals from outside, first, second and third input buffers respectively coupled to the first, second and third terminals, the first, second and third input buffers producing first, second and third buffered signals responsive to the first, second and third input signals, respectively, and first and second gate circuits respectively coupled to the first and second input buffers, the first and second gate circuits coupled to the third input buffer in common, the first and second gate circuits respectively driving output nodes thereof in response to the first and second buffered signals when the third buffered signal is activated, and each of the first and second gate circuits holding the output nodes thereof at a fixed level irrelatively to the first and second buffered signals when the third buffered signal is inactivated.