SRAM Cell Segmentation for Disturb-Free Operation
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Solution Overview
Problem
Conventional SRAM cells face challenges with increased variability in transistor electrical characteristics at sub-micron scales, leading to read and write failures, and a tradeoff between cell stability and write margin, which becomes increasingly difficult with device feature size scaling.
Innovation Solution
The implementation of a static random access memory (SRAM) cell with two complementary latched storage nodes, a read buffer gated by a read word line, and a write element that sets the latched state using complementary write bit lines and a write select transistor gated by a write word line, isolating storage nodes from write voltages during read cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional 6-T SRAM cell design is used, then device feature size can be scaled down, but cell stability deteriorates and disturb vulnerability increases
Solution Approach 1:
The SRAM cell is segmented into distinct functional blocks: storage element (cross-coupled inverters), read buffer (separate from storage), and write element (separate from storage). This segmentation isolates the storage nodes from read and write operations, preventing disturb while maintaining stability even at scaled feature sizes
Solution Approach 2:
The read buffer and write element are extracted as separate functional units from the storage element. The read buffer includes transistors connected to storage nodes but electrically isolated during non-read operations. The write element includes transistors that can force storage nodes to desired states without disturbing them during read operations
2Reliability
If pass transistor drive is increased to improve write margin, then write capability improves, but cell stability deteriorates
Solution Approach 1:
The read buffer pass transistors are dynamically controlled by the read word line, being conductive only during read operations. The write element transistors are dynamically controlled by write word lines, being conductive only during write operations. This dynamic control allows strong drive during operations without compromising storage stability during idle periods
Solution Approach 2:
The read and write operations are performed periodically and selectively, with read word lines and write word lines activating respective transistors only when needed. This periodic activation ensures that strong transistor drive is available when required for reads and writes, while the storage element remains undisturbed during non-operational periods
Data Source
AI summary
A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.