Semiconductor Memory Input Circuit Rank Configuration

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Solution Overview

Problem

Conventional semiconductor memory external signal input circuits are designed for either single-rank or multi-rank configurations, limiting their adaptability and requiring separate circuit designs for different configurations.

Innovation Solution

An external signal input circuit for semiconductor memory that includes an input block to receive and generate internal signals and a control block to output signals corresponding to the rank configuration, while blocking signals that do not match the configuration, allowing the same circuit to function in both single-rank and multi-rank configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate external signal input circuits are designed for single-rank and multi-rank configurations, then each circuit can be optimized for its specific configuration, but the device complexity increases and adaptability decreases

Engineering Contradiction:
Improvecircuit optimization for specific configurationVSAvoidmultiple separate circuit designs
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The external signal input circuit is designed with a universal structure that can function in both single-rank and multi-rank configurations. The circuit includes a first input unit for receiving external signals and a second input unit that can be selectively activated based on rank configuration. A control unit manages the selection between different input units, allowing the same circuit hardware to adapt to different memory configurations without requiring separate dedicated circuits for each rank type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a universal external signal input circuit is designed to work in both single-rank and multi-rank configurations, then adaptability improves, but the circuit complexity increases

Engineering Contradiction:
Improvecircuit compatibility across configurationsVSAvoidcircuit structure for multiple configurations
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The external signal input circuit is segmented into distinct functional units: a first input unit for receiving external signals, a second input unit for additional signal processing, and a control unit for managing operation modes. This segmentation allows the circuit to activate only the necessary units based on the detected rank configuration, reducing the effective complexity in any given operation while maintaining universal adaptability across different memory configurations.

Inventive Principle:
Principle #1Segmentation

3Reliability

If different external signal input circuits are used for different rank configurations, then signal processing can be optimized for each configuration, but the ease of manufacture decreases

Engineering Contradiction:
Improvesignal processing optimizationVSAvoidproduction of multiple circuit variants
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent implements a universal external signal input circuit design that eliminates the need to manufacture separate circuit variants for single-rank and multi-rank configurations. The same circuit hardware is produced for all memory devices, with the control unit automatically configuring the circuit operation based on the detected rank configuration. This approach significantly simplifies the manufacturing process while maintaining optimized signal processing through selective activation of appropriate input units and control logic.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8335124B2External signal input circuit of semiconductor memory
Publication Date: 2012.12.18 MIMIRIP LLC
  • US8335124B2 patent drawing
  • US8335124B2 patent drawing
  • US8335124B2 patent drawing

AI summary

In one embodiment, an external signal input circuit of a semiconductor memory may include: an input block configured to receive a plurality of external signals and to generate a plurality of internal signals; and a control block configured to output one or more internal signals of the plurality of internal signals that correspond to a rank configuration of the semiconductor memory and to block output of one or more internal signals of the plurality of internal signals that do not correspond to the rank configuration.