Write Assist Circuit for Memory Cell Disturb Control
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Solution Overview
Problem
Write disturb issues in memory cells cause increased power consumption and reduced functionality when write assist circuits are constantly activated, even in the absence of disturbances, leading to inefficient operation and reduced memory cell lifetime.
Innovation Solution
A circuit that detects write disturbs and activates the write assist circuit only when a disturbance occurs, thereby reducing power consumption and minimizing stress on the memory cell by ensuring the write assist circuit remains off during undisturbed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write assist circuit is turned on every time the memory cell is write-accessed, then the write operation can function at VDDmin value, but the power consumption of the memory cell increases
Solution Approach 1:
The write assist circuit is made dynamic by introducing a disturb detection mechanism that monitors whether a dummy read operation is simultaneously accessing the same memory cell. The circuit transitions between active and inactive states based on the detected disturbance condition, allowing it to adapt its power consumption to actual operational needs rather than remaining constantly active
Solution Approach 2:
The system uses the existing read-write port infrastructure and control signals to detect write disturb conditions. The disturb detection logic utilizes the same control lines and timing signals already present in the memory cell architecture, allowing the system to self-monitor and self-regulate write assist activation without requiring external intervention or additional complex control mechanisms
2Reliability
If the write assist circuit is constantly activated to handle write disturb conditions, then the memory cell can operate reliably during disturbed writes, but the lifetime of the memory cell is reduced due to increased stress
Solution Approach 1:
The write assist circuit activation is made conditional and dynamic rather than static and constant. By implementing disturb detection that monitors the simultaneous access of read-write ports, the circuit only activates when actually needed to correct write disturb conditions. This dynamic approach reduces unnecessary stress cycles on the memory cell, thereby extending its operational lifetime while maintaining reliability when disturbances do occur
3Reliability
If the write assist circuit is activated to improve write operation at VDDmin, then the minimum supply voltage requirement is met, but the operational efficiency is reduced due to unnecessary activation
Solution Approach 1:
The system employs self-monitoring capabilities using existing control signals and port status information to automatically detect when write disturb conditions occur. This self-service approach allows the write assist circuit to activate only when genuinely needed, eliminating unnecessary activations that would reduce operational efficiency while ensuring reliability when actual disturbances occur
Solution Approach 2:
A feedback mechanism is introduced where the status of read-write port accesses is continuously monitored and fed back to the write assist control logic. This feedback allows the system to make real-time decisions about write assist activation based on actual disturbance conditions, optimizing the balance between maintaining VDDmin operation reliability and preserving operational efficiency
Data Source
AI summary
A circuit comprises a first memory cell, a second memory cell, and a disturb control circuit. The first memory cell has a first port and a second port. The first port is associated with a first write assist circuit. The second port is associated with a second write assist circuit. The second memory cell has a third port and a fourth port. The third port is associated with a third write assist circuit. The fourth port is associated with a fourth write assist circuit. The disturb control circuit is configured to selectively turn on at least one of the first write assist circuit, the second write assist circuit, the third write assist circuit, or the fourth write assist circuit according to whether the first port, the second port, the third port, or the fourth port is determined to be write disturbed.