SRAM Assist Circuits for Low-Voltage Defect Detection
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Solution Overview
Problem
The increasing static power consumption in CMOS circuits, particularly in embedded memories of system-on-chips, due to subthreshold leakage currents, poses a significant design challenge, and conventional memory cell testing methods fail to detect defects until they become large, leading to inefficient defect identification and potential faulty behaviors.
Innovation Solution
The implementation of Word Line Reduction (WLR) and Negative Bit Line (NBL) boost assist circuits, which modify voltages in SRAM core-cells to detect resistive-open and resistive-bridging defects, enhancing the detection of faulty behaviors and improving read and write margins, thereby minimizing time complexity and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional memory cell testing methods are used, then test simplicity is maintained, but defect detection capability deteriorates (defects only detected when large)
Solution Approach 1:
The patent introduces assist circuits as intermediary components that connect to the SRAM core-cell array to provide enhanced testing capability. These assist circuits include test control logic and measurement circuits that mediate between the test stimulus and the memory cells, enabling detection of small defects through voltage monitoring and comparison operations.
Solution Approach 2:
The patent implements preliminary testing actions by first applying test patterns to the SRAM core-cell array before actual operation. The test control circuit prepares test conditions in advance, including setting up assist circuit configurations and pre-charging test structures, so that defect detection can be performed systematically before the memory is deployed.
2Area of moving object
If technology scaling is applied to shrink device features, then integration density is improved, but static power consumption increases due to subthreshold leakage currents
Solution Approach 1:
The patent changes operating parameters by implementing voltage scaling techniques and modifying the threshold voltage of transistors through assist circuitry. The test control circuit adjusts voltage levels dynamically during testing to reduce subthreshold leakage current while maintaining sufficient signal margins for defect detection, thereby addressing the power consumption issue arising from technology scaling.
3Measurement precision
If assist circuits are added to enhance defect detection, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent designs assist circuits with multi-functionality to reduce overall complexity. The test control circuit performs multiple functions including pattern generation, voltage monitoring, assist circuit control, and result comparison. The same assist circuit infrastructure is used for both testing and operational modes, allowing a single circuit to serve multiple purposes and thereby reducing the net complexity increase.
4Measurement precision
If conventional testing is used without assist circuits, then area overhead is minimized, but defect detection coverage is insufficient (up to 89% of defects undetected)
Solution Approach 1:
The patent implements a nested structure where the assist circuits are integrated within or alongside the SRAM core-cell array. The test control circuit is nested within the memory structure, with assist circuits positioned to directly interface with the core-cell array. This nesting approach allows enhanced defect detection coverage while minimizing the additional area required, as the test infrastructure shares space with the operational memory structure.
Data Source
AI summary
Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist techniques improve read stability and write margin of SRAM core-cells, respectively, when the memory operates at a lowered supply voltage. Assist circuits are activated at particular points in the memory cell circuit. The assist circuits are selectively activated for modifying the voltage along particular circuit elements to identify the potential defects that might be otherwise masked until substantially large. A March test invokes elements for activating the assist circuits to identify defects and indicate functional fault models (FFMs) associated with the defects.