Non-volatile Memory Device Sequential Far-to-Near Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance change memory devices face issues with increased consumption current and error settings or resettings due to leak currents to non-target memory cells or wiring resistance during forming, setting, and resetting operations.
Innovation Solution
The non-volatile semiconductor memory device employs a configuration where the forming, setting, and resetting operations are performed sequentially from the memory cell on the Far side to the Near side, reducing leak current and optimizing voltage application to maintain data integrity and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If forming, setting, and resetting operations are performed simultaneously across all memory cells, then processing speed is improved, but consumption current increases and errors occur due to leak current to non-target cells
Solution Approach 1:
The patent divides the memory cell array into multiple groups along the bit line direction and performs forming, setting, and resetting operations on these groups sequentially rather than simultaneously. This segmentation reduces the number of cells experiencing high current at any given time, thereby reducing consumption current while maintaining processing efficiency through systematic batch processing.
Solution Approach 2:
The patent performs forming operations on memory cells before setting and resetting operations. By pre-forming the variable resistance elements to establish proper current paths and reduce leakage, the subsequent setting and resetting operations experience reduced leak current, enabling faster and more accurate data storage without excessive power consumption.
2Productivity
If high voltage is applied to all memory cells simultaneously for forming operation, then forming speed is improved, but error setting or resetting occurs due to leak current to non-target cells
Solution Approach 1:
The patent segments the memory cell array into multiple groups along the bit line direction and applies forming voltage to these groups sequentially. This ensures that high voltage is applied to only one group at a time, preventing leak current from affecting non-target cells and eliminating error setting or resetting while maintaining fast forming speed through systematic processing.
Solution Approach 2:
The patent performs forming operations as a preliminary step before setting and resetting operations. By pre-forming the variable resistance elements to establish proper current paths and reduce leakage, the subsequent setting and resetting operations experience reduced leak current, preventing errors while maintaining data integrity.
3Reliability
If sequential operation from Far side to Near side is implemented, then leak current is reduced and data integrity is improved, but processing time increases
Solution Approach 1:
The patent segments the memory cell array into multiple groups along the bit line direction and processes these groups sequentially from the Far side to the Near side. This segmentation allows for systematic voltage application that reduces leak current and improves data integrity while minimizing processing time through efficient batch processing of multiple cells within each group.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes errors and power consumption by controlling voltage distribution effectively across the memory cell array, ensuring accurate data storage and retrieval without increasing the cell array area.
Implementation Method 1
a voltage applying circuit which is connected to one of the first decoder and the second decoder and which applies a predetermined voltage between the first lines and the second lines selected by the first decoder and the second decoder
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first and second decoders and which applies a predetermined voltage between the first and second lines selected by the first and second decoders. The second decoder sequentially selects the second lines in a direction from the other ends to the one ends of the first lines.