Resistive Memory Device Shared Power Path
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Solution Overview
Problem
Resistive memory devices face challenges in reducing chip size due to the need for separate power paths for write and read operations, which increases the chip size and complicates memory operations.
Innovation Solution
A resistive memory device with a voltage generator for generating write and read word line voltages, a switch circuit to manage these voltages, and a word line driver that performs write and read operations using a common power path, allowing for integrated power management and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate power paths are used for write and read operations, then power management is simplified, but chip size increases
Solution Approach 1:
The patent merges separate write and read power paths into a single shared power path. The word line driver circuit is configured to supply power for both write operations (via write word line voltage) and read operations (via read word line voltage) through the same physical power path, eliminating redundant power distribution circuits and reducing chip area.
Solution Approach 2:
The word line driver circuit is designed with multi-functionality to handle both write and read operations through a single power path. The circuit can selectively output either write word line voltage or read word line voltage based on the operation type, making the power path universal for both functions without requiring separate dedicated paths.
2Area of stationary object
If a single power path is used for write and read operations, then chip size is reduced, but power management complexity increases
Solution Approach 1:
The word line driver circuit acts as an intermediary between the shared power path and the memory cell array. It receives a single power supply voltage and internally generates the appropriate write or read word line voltages based on control signals, thereby managing the complexity of voltage generation and switching within a single integrated circuit block rather than requiring separate power distribution networks.
Solution Approach 2:
The power path configuration is made dynamic through the word line driver circuit's ability to switch between different voltage output modes (write mode or read mode) based on operational requirements. This dynamic switching capability allows a single static power path to serve multiple functional purposes, reducing hardware complexity while maintaining operational flexibility.
3Productivity
If write word line voltage is generated during write enable signal activation, then write operation timing is controlled, but read operation flexibility is reduced
Solution Approach 1:
The word line driver circuit implements dynamic voltage output based on the type of operation requested. During write operations, it generates write word line voltage synchronized with the write enable signal for precise timing control. During read operations, it switches to generating read word line voltage that can be applied flexibly without being constrained by write enable signal timing, thus adapting to different operational modes.
Solution Approach 2:
The circuit changes its output voltage parameters (voltage level, timing characteristics) based on the operation type. For write operations, it outputs write word line voltage with specific timing relative to the write enable signal. For read operations, it outputs read word line voltage with different timing characteristics, allowing read operations to occur independently of write enable signal activation periods.
Data Source
AI summary
A resistive memory device includes: a voltage generator generating a write word line voltage according to activation of a write enable signal; a switch circuit outputting one of the write word line voltage and a read word line voltage in response to the write enable signal as an output voltage; a word line power path connected to the switch circuit to receive the output voltage; and a word line driver driving a word line according to a voltage applied to the word line power path, wherein a write command starts to be received after a certain delay following the activation of the write enable signal, and a write operation is performed within an activation period of the write enable signal in response to the received write command.