Read Assist Circuitry for Memory Cell Stability
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Solution Overview
Problem
Conventional memory cells experience instability during read operations due to charge injection from bitline capacitance, leading to read disturb issues, which can cause unintended state switching.
Innovation Solution
An area-efficient read assist scheme using write assist circuitry, such as negative bitline write assist, where charge is recirculated to precharge the bitline to a reduced voltage, reducing charge injection and implementing read assist circuitry to share charge between bitlines and write assist circuitry for ultra-low power memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cells are used during read operations, then the memory cell can store data, but charge injection from bitline capacitance causes the internal node bias to rise above the switching point, making the memory cell unstable and causing read disturb
Solution Approach 1:
The patent applies preliminary action by pre-charging the bitline to a reduced voltage level (VDD-x) before the read operation begins. This is achieved by recirculating charge collected during write assist operations to charge the bitline capacitor. By preparing the bitline in advance with reduced voltage, the harmful charge injection effect is prevented before it can occur during the read operation, thus maintaining memory cell stability.
Solution Approach 2:
The patent changes the voltage parameter of the bitline from the conventional VDD level to a reduced voltage level (VDD-x). This parameter change is achieved by controlling the charge sharing between the bitline capacitor and the write assist capacitor through timing control of the first transistor. By operating the bitline at a lower voltage during read operations, the charge injection into the memory cell is reduced, preventing read disturb while maintaining adequate signal swing for successful reads.
2Reliability
If write assist circuitry is dedicated only to write operations, then write operations can be assisted, but separate read assist circuitry would be needed for read operations, increasing device complexity and area
Solution Approach 1:
The patent applies universality by enabling the write assist capacitor to serve dual purposes: assisting write operations and assisting read operations. The same capacitor that stores charge for negative bitline write assist is also used to pre-charge the bitline for read operations by controlling the charge sharing through the first transistor. This eliminates the need for separate read assist circuitry, reducing device complexity and area while maintaining adequate assist for both read and write operations.
Solution Approach 2:
The patent applies discarding and recovering by recirculating the charge that was collected in the write assist capacitor during write operations. Instead of dissipating this charge or using it only for write operations, the system recovers and reuses it to pre-charge the bitline for subsequent read operations. This charge recycling approach enables the same hardware resource to provide assist for both read and write operations, reducing overall circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves access disturb margin by reducing read disturb and reuses write assist circuitry for read operations, enhancing the stability of memory cells and reducing power consumption.
Implementation Method 1
charge collected during an assist operation may be recirculated for charging a discharged bitline
Implementation Method 2
implementing read assist circuitry to share charge between bitlines and write assist circuitry
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.