Built-in Test Circuit for Semiconductor Memory Burn-in
Solution Overview
Problem
Conventional burn-in stress tests for semiconductor memories are time-consuming once the memory is packaged, requiring efficient methods for early detection of defects during the wafer testing stage.
Innovation Solution
Integration of a built-in test circuit within the semiconductor memory that includes a controller, multiplexers, and decoders to generate test addresses and control signals, enabling simultaneous testing of multiple rows and columns during the burn-in stress test, thereby reducing testing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If burn-in stress tests are performed after packaging, then defect detection is achieved, but testing time is excessive
Solution Approach 1:
The patent implements a built-in test circuit that performs burn-in stress testing before the memory device is packaged. The test circuit includes address generators, decoders, and data write/read circuits that are integrated into the memory device itself, allowing stress testing to be conducted on the wafer level before packaging, thereby reducing the time required for post-packaging testing while maintaining defect detection capability
Solution Approach 2:
The memory device performs self-testing through the built-in test circuit that is integrated within the device structure. The test circuit uses the memory device's own address decoders, data buffers, and memory cells to conduct stress testing, eliminating the need for external testing equipment and reducing testing time while maintaining comprehensive defect detection
2Productivity
If multiple rows and columns are tested simultaneously, then testing speed is improved, but device complexity increases
Solution Approach 1:
The built-in test circuit is designed to use the same address decoders, data buffers, and memory cell structures that are used during normal memory operation. The address generators and control logic are integrated with the existing memory architecture, allowing the circuit to serve both normal operation and testing functions, thereby increasing testing speed without significantly increasing device complexity
Solution Approach 2:
The test circuit dynamically activates multiple rows and columns simultaneously by generating multiple address signals in parallel. The address generators produce address sequences that activate different memory regions concurrently, and the control logic dynamically manages the simultaneous operations, thereby improving testing speed while utilizing the existing flexible memory architecture
Data Source
AI summary
A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type.