Bulk and SOI Device Integration via Common Gate Height
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Solution Overview
Problem
The cointegration of bulk and SOI semiconductor devices poses challenges due to topology issues and complexity in integration processes, particularly with the step height difference between SOI and bulk substrates, which complicates the formation of channel silicon germanium layers and reliable encapsulation of high-k materials during fabrication.
Innovation Solution
The formation of semiconductor devices with bulk and SOI structures of a common height level by removing the semiconductor and buried insulation layers in one region and maintaining them above the bulk substrate in another, allowing for gate structures to extend to a unified height, facilitating the integration of resistor, capacitor, or FET devices on both substrates using gate-first or gate-last techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are miniaturized into the deep submicron regime, then device performance and integration density are improved, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent divides the semiconductor substrate into distinct SOI regions and bulk regions, allowing different device types to be fabricated in separate zones. This segmentation enables specialized process optimization for each region type while maintaining overall integration density, as each region can be processed independently with appropriate techniques for its specific requirements.
Solution Approach 2:
The invention implements local quality by providing different substrate structures (SOI vs. bulk) in different regions of the same semiconductor device. This allows threshold voltage and other electrical characteristics to be locally optimized for specific device requirements, while maintaining consistent miniaturization across the entire chip to preserve integration density.
2Adaptability or versatility
If SOI and bulk devices are cointegrated on the same substrate, then device functionality and versatility are improved, but topology issues and integration process complexity arise
Solution Approach 1:
The patent segments the substrate into SOI regions and bulk regions that are spatially separated and clearly defined. This segmentation allows each region type to be processed using appropriate techniques without interfering with the other, eliminating topology issues that would arise from attempting to integrate SOI and bulk devices in the same local area while still achieving functional versatility through cointegration.
Solution Approach 2:
The invention uses carefully engineered transition regions between SOI and bulk areas as intermediaries that manage the interface between the two different substrate types. These transition zones are designed to minimize stress concentration and process conflicts, allowing seamless integration of both device types without requiring overly complex integration processes.
3Reliability
If threshold voltage variations are reduced for well-defined switching characteristics, then device performance is improved, but fabrication process adjustment and fine-tuning complexity increase
Solution Approach 1:
The patent employs local quality by implementing different substrate structures (SOI versus bulk) in different regions to achieve desired threshold voltage characteristics. SOI devices in specific regions provide reduced threshold voltage variations and improved switching characteristics, while bulk devices in other regions can be optimized for different requirements, eliminating the need for complex process fine-tuning across the entire chip.
Data Source
AI summary
An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.