Wafer-Scale Bumpless Device Assembly via Pre-Formed Conductive Pads
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Solution Overview
Problem
Conventional flip-chip packaging methods are equipment intensive, environmentally unfriendly, and inefficient, with long cycle times and high costs, and they require wafer dicing outside the clean room environment, leading to increased manufacturing costs and reliability issues due to thermal stress.
Innovation Solution
A semiconductor chip with added conductive layers on contact pads for direct bonding to a wiring board using metallic interdiffusion, conductive adhesives, or solder paste, allowing for wafer-scale assembly in a clean room environment, reducing equipment costs and improving thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-chip assembly with solder bumps is used, then electrical connection is achieved, but equipment cost and manufacturing complexity increase significantly
Solution Approach 1:
The patent extracts the solder bump formation process from the assembly sequence by pre-forming metal pads on the wafer before dicing. This eliminates the need for complex post-dicing solder bumping equipment while maintaining reliable electrical connections through direct metal-to-metal bonding or solder attachment to the pre-formed pads.
Solution Approach 2:
The patent performs the metal pad formation action in advance during wafer fabrication, before the chips are diced. This preliminary action eliminates the need for expensive post-assembly solder bumping equipment and reduces manufacturing complexity while ensuring reliable electrical connections are established.
2Reliability
If conventional solder bump processes are used, then electrical connection is achieved, but environmental harm and processing cost increase
Solution Approach 1:
The patent replaces expensive and environmentally harmful lead-containing solder materials with simpler, lead-free metal pads that can be formed during wafer fabrication. This eliminates the need for complex soldering processes and reduces environmental harm while maintaining reliable electrical connections.
3Ease of manufacture
If wafer dicing is performed outside clean room, then chip assembly can proceed, but manufacturing cost and reliability increase due to contamination
Solution Approach 1:
The patent performs the metal pad formation action in advance during wafer fabrication in the clean room environment. This preliminary action allows the entire wafer to be processed and prepared under controlled clean room conditions before dicing, eliminating the need to perform subsequent assembly steps outside the clean room and reducing contamination risks.
4Reliability
If conventional reflow processes are used, then solder bonding is achieved, but manufacturing time and energy consumption increase
Solution Approach 1:
The patent extracts the bonding function from the conventional reflow process by using pre-formed metal pads that can be directly bonded to the substrate through simpler, faster processes. This eliminates the need for long-duration reflow cycles while maintaining reliable bonding through direct metal-to-metal contact or simplified solder attachment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, eliminates lead usage, enhances thermal performance, and improves reliability by enabling lead-free assembly and thin chip-scale device fabrication with reduced thermomechanical stress.
Implementation Method 1
The bonding is performed by a technique selected from Direct welding by metallic interdiffusion; Attaching by solder paste; Attaching by conductive adhesive
Implementation Method 2
this plate has a thickness compatible with the thickness of the conductive pad layer
Data Source
AI summary
A semiconductor chip having a planar active surface including an integrated circuit; the circuit has metallization patterns including a plurality of contact pads. Each of these contact pads has an added conductive layer on the circuit metallization. This added layer has a conformal surface adjacent the chip and a planar outer surface, and this outer surface is suitable to form metallurgical bonds without melting. The chip contact pads may have a distribution such that an area portion of the active chip surface is available for attaching a thermally conductive plate; this plate has a thickness compatible with the thickness of the conductive pad layer.