Bumpless Wafer Level Fan-Out Package Thickness Reduction
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Solution Overview
Problem
Flip chip semiconductor packages with interposer substrates are excessively thick, leading to high assembly costs, low manufacturing yield, and production inefficiencies due to pitch mismatch and degraded signal integrity.
Innovation Solution
A bumpless wafer level fan-out package is created by directly coupling conductive pads on an integrated circuit die to corresponding pads on an interposer substrate, eliminating the need for solder bumps and allowing for a compact, thin package structure with interconnect pathways for high-density signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used to electrically couple the integrated circuit die to the interposer substrate, then electrical connection is achieved, but the package thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent removes the solder bumps from the electrical coupling process, extracting the problematic intermediate element that causes increased package thickness. Instead, direct pad-to-pad contact is established between the integrated circuit die and interposer substrate, eliminating the thickness contribution of bumps while maintaining reliable electrical connection.
Solution Approach 2:
The patent employs asymmetric pad design where the contact pads on the integrated circuit die and interposer substrate are configured with different geometries and positions to enable direct contact without requiring symmetric bump structures. This asymmetric approach allows for thinner package design while ensuring proper electrical alignment and connection.
2Reliability
If solder bumps are used for mounting the integrated circuit die, then electrical coupling is achieved, but the package structure becomes complicated resulting in high assembly cost
Solution Approach 1:
The patent extracts and eliminates the solder bump structure from the package design, removing the complexity associated with bump formation, alignment, and assembly processes. The simplified direct pad contact approach reduces structural complexity while maintaining electrical coupling functionality.
Solution Approach 2:
The patent merges the electrical connection function directly into the pad contact interface, eliminating the need for separate bump structures. This consolidation of functions reduces package structural complexity and assembly steps while achieving reliable electrical coupling between the die and substrate.
3Reliability
If interposer substrate is used with bumped integrated circuit die, then electrical connection is achieved, but pitch mismatch and signal integrity degradation occur
Solution Approach 1:
The patent removes the solder bumps that cause pitch mismatch issues, replacing them with direct pad contact that can be precisely aligned during the wafer-level processing stage. This extraction eliminates the pitch mismatch problem while maintaining electrical connection reliability.
Solution Approach 2:
The patent performs preliminary alignment and pad configuration during the wafer-level fabrication process before final assembly. This preliminary action ensures precise pad positioning and matching, preventing pitch mismatch and signal integrity degradation that would occur with post-assembly bump alignment.
Data Source
AI summary
An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an integrated circuit die. The second conductive pad may directly contact the first conductive pad on the interposer substrate. The integrated circuit package may further include a package substrate having a cavity, in which the interposer substrate and the integrated circuit are disposed in the cavity. The interposer substrate may include interconnect pathways that are electrically coupled to the first and second conductive pads. A heat spreader may subsequently form over the integrated circuit die and the package substrate.