Buried Bit Line Vertical Transistor for Memory Density
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Solution Overview
Problem
The narrow channel effect and short channel effect, resulting from the reduction in transistor channel size, degrade transistor performance and limit the further improvement of memory storage density.
Innovation Solution
A semiconductor structure is formed by providing a substrate with a sacrificial layer and an active layer, etching to create active lines, forming isolation layers, and replacing the sacrificial layer with a conductive bit line to facilitate the formation of a vertical transistor, allowing for increased storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of the transistor is reduced to decrease the size of the transistor, then the storage density of the memory is increased, but the transistor performance is degraded due to narrow channel effect and short channel effect
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the vertical direction through the active layer, enabling smaller footprint transistors while maintaining adequate channel length for performance, thus resolving the contradiction between storage density and transistor performance
Solution Approach 2:
The vertical transistor structure nests the channel within the active layer column, with the channel extending vertically through the active layer. The bit line is formed by removing the sacrificial layer and filling the resulting space, creating a nested configuration where the conductive path is integrated within the vertical structure, achieving both compact size and functional performance
2Productivity
If the channel size is reduced to increase storage density, then more transistors can be integrated, but the narrow channel effect and short channel effect degrade device performance
Solution Approach 1:
By orienting the channel vertically rather than horizontally, the patent achieves higher integration density in the planar direction while maintaining sufficient channel length vertically. This dimensional change allows multiple vertical transistors to be packed closely in the horizontal plane without sacrificing channel length, thereby improving integration density while preserving device performance
3Quantity of substance
If planar transistors are used with reduced channel size, then storage density increases, but further improvement is limited by performance degradation
Solution Approach 1:
The vertical transistor architecture provides a new dimensional approach that overcomes the limitations of planar scaling. By extending the channel vertically, the design enables continued improvement in storage density without being constrained by the performance degradation that occurs in planar geometries at small dimensions, thus restoring adaptability for further enhancement
Data Source
AI summary
A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.