Digital Storage TRIZ Cases

A bit line voltage control circuit detects current flow in ReRAM arrays to dynamically adjust line voltages.

A semiconductor memory device uses pin selection signals to control termination resistors in input output buffers.

Pre-charging bit lines establishes a common reference potential that reduces threshold mismatch impact, improving read accuracy.

A memory device uses a repair circuit to shift data lines and replace defective cells in a common redundant region.

A mixed memory cell architecture segments word lines into 1T and 2T regions to enhance access speed.

Alternating X and Y decoder layers between memory groups reduces circuit arrangement complexity while increasing integration density.

A three-state spintronic device switches resistance states via spin-orbit torque to enable efficient neural network operations.

Segmented RF network nodes in a passive RFID tag increase bandwidth and reliability without requiring local power.

A memory controller moves data between sections using sense amplifiers and buffer rows.

Destructive write-back circuits restore disturbed magnetic states after reading, enabling higher read voltages without degrading stored data.

Voltage boost lines create coupling capacitances with wordlines to dynamically adjust voltage levels during memory operations.

Varying the common-mode voltage on shared signal paths transmits logical control signals alongside data, reducing device complexity without adding wires.

A multi-port memory device uses a clock generator to produce internal signals for local port access.

Shaped data adjusts neighboring storage element resistance to control leakage current variability, improving data storage reliability.

Over-sampling read memory controllers perform internal threshold detection to reduce error correction latency and energy consumption.

A memory device detects internal potential failures by floating unselected sub-wordline decoders and reading data through sense amplifiers.

Segmented monitor logic identifies leakage current to reduce standby power consumption.

An access counter tracks memory block operations to trigger periodic word line activation, reducing power consumption during irregular data access.

Replacing sacrificial layers with conductive bit lines enables vertical transistors that overcome narrow channel effects and boost integration density.

Segmenting the decoder into monotonic and generalized parts reduces wordline generation delay by minimizing AND gate count in the critical path.

A dynamic power supply voltage adjustment system drops memory cell voltage below retention levels during write operations to improve transistor contention.

A temporal calibration mechanism determines data eye boundaries using minimal tests to reduce resource consumption.

A memory device selects between data queue strobe and system clock signals to initiate data receipt.

Read verify circuits mediate between STT-MRAM arrays and outputs, resolving read decision failures caused by process variations.

Parallel control devices eliminate sequential transmission delays by synchronizing data and control signals within a precise timing window.

A magnetic memory design applies voltage to a nonmagnetic conductor to manipulate magnetic anisotropy and control domain wall movement.

A reservoir capacitor design reduces domain crossing noise between heterogeneous power supplies using serially coupled groups and interconnecting lines.

Charge sharing controls gate voltage in a CMOS synaptic array, maintaining consistent weight update characteristics across the crossbar structure.

A semiconductor memory device uses a data coding unit to minimize first logic state bits during initial operations.

A ReRAM controller stores volatile data during power loss using a write-amplifier queue to preserve information without external capacitors.

A common write driver reduces semiconductor memory area by sharing drive circuits between banks, lowering production costs.

Rail isolators between inverters and potential rails increase noise immunity, preventing data loss at ultra-low supply voltages.

Dynamic voltage transitions resolve the contradiction between precharge reliability and sensing margin, improving read operation speed.

Connecting two two-port memories creates a three-port structure that eliminates unnecessary circuits and reduces circuit area.

Priority encoder identifies next empty cell location in store cell memory, reducing traffic stall time during sequential-write operations.

A state machine synchronizes data strobe input buffer enablement with clock signals to ensure deterministic timing.

A semiconductor memory apparatus uses a control signal generation part to drive an output circuit for flexible test data handling.

Distributing control circuit instances across sub-holes and array regions to minimize noise from long interconnects.

A DRAM architecture selectively enables specific page areas based on column address bits to reduce unnecessary power usage.

Biasing adjacent conductive lines suppresses leakage current to unselected cells, improving sensing margin without increasing power consumption.

Training method applies conductance error noise to neural network weights, maintaining accuracy despite memristive device variability.

Series-parallel magnetic tunnel junction arrays amplify output signals while maintaining low coupling capacitance for extended frequency responses.

A voltage clamp with a semiconductor switch constrains bit line excursions, preventing voltage spikes that degrade non-volatile memory reliability.

Alternating polarity pulse sequences program memristive devices by managing resistive heating and reducing net dopant drift during switching operations.

A semiconductor memory apparatus uses a temperature sensor and refresh controller to adjust execution cycles for volatile memory cells.

Segmented auto-precharge signal generator circuit prevents abnormal pulse generation during burst operations by controlling timing margins.

Sidewall spacers align magnetic tunnel junction pillars with spin-orbit torque lines, eliminating current circumvention and enhancing switching efficiency.

A magnetic random access memory re-routes digitline current through a selected bitline to generate shared magnetic fields.