In-Memory Computing STT-MRAM Read Verify Circuit
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Solution Overview
Problem
Current on-chip Spin Transfer Torque Magnetic RAM (STT-MRAM) memory systems face inefficiencies due to process variations and stochastic nature, leading to challenges in performing effective in-memory computing, particularly in enabling multiple word lines and addressing retention and read decision failures.
Innovation Solution
A novel architecture and method for in-memory computing using a matrix of bit cells with an address decoder and sensing circuits, enabling simultaneous activation of multiple word lines and computation operations within the STT-MRAM array, leveraging the resistive nature of STT-MRAM cells to perform logic functions and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are activated simultaneously for in-memory computing, then computation capability is improved, but process variations and stochastic nature of STT-MRAM cause read decision failures
Solution Approach 1:
A read verify circuit is introduced as an intermediary between the STT-MRAM array and the output. This circuit performs read verification by checking whether read data meets predetermined criteria before outputting results, thereby compensating for read decision failures caused by process variations and stochastic behavior during multi-word line operations
Solution Approach 2:
The read verify circuit implements a feedback mechanism where read data is continuously monitored and verified against predetermined criteria. If the read data does not meet the criteria, the system can retry or correct the operation, ensuring reliable computation results even when process variations affect the stochastic STT-MRAM cells
2Use of energy by moving object
If multiple word lines are activated for compute-in-memory operations, then energy efficiency is improved, but retention failures occur due to prolonged activation
Solution Approach 1:
The system employs periodic read verification operations during multi-word line activation. Instead of continuous monitoring, the read verify circuit periodically checks data integrity at critical points in the computation process, allowing multiple word lines to remain activated for energy-efficient computation while periodically ensuring data retention through verification
Solution Approach 2:
The read verify circuit performs preliminary verification of read data before it is used in subsequent computation steps. By checking data integrity in advance, the system prevents propagation of errors from retention failures while maintaining the energy benefits of prolonged word line activation
3Area of stationary object
If on-chip STT-MRAM is used for in-memory computing, then integration density is improved, but process variations make computation unreliable
Solution Approach 1:
The read verify circuit serves as a mediator between the high-density but variation-prone STT-MRAM array and the computation logic. It verifies read data against predetermined criteria and can trigger retries or corrections, ensuring computation reliability without sacrificing the integration density benefits of on-chip STT-MRAM
Solution Approach 2:
The system dynamically adjusts verification parameters and computation parameters based on process conditions. The read verify circuit can modify verification thresholds and the system can adjust computation parameters to compensate for process variations, maintaining reliable computation across different manufacturing conditions while preserving high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the energy efficiency and performance of on-chip STT-MRAM by reducing read disturb failures and enabling efficient computation within memory structures, while maintaining data integrity through error correction mechanisms.
Implementation Method 1
leveraging the resistive nature of STT-MRAM cells to perform logic functions
Data Source
AI summary
A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.