Semiconductor Memory Page Buffer Sensing Signal Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently performing read operations due to limitations in data sensing mechanisms, particularly in maintaining accurate voltage levels and sensing currents, which affect the reliability and speed of data retrieval.
Innovation Solution
The semiconductor memory device incorporates a memory cell array coupled with page buffers and control logic that generate a page buffer sensing signal, transitioning from a first to a second voltage level after precharging, allowing for effective data sensing by adjusting the voltage levels and current flow through bit lines, thereby improving sensing margin and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the page buffer sensing signal voltage is maintained at a high level during precharge, then the internal node can be properly precharged, but the sensing margin is reduced during actual sensing
Solution Approach 1:
The page buffer sensing signal is applied in two distinct voltage levels at different times: a first voltage level during precharge and a second voltage level during sensing. This periodic voltage adjustment allows the system to optimize for precharge reliability first, then for sensing margin, resolving the contradiction between these two requirements.
Solution Approach 2:
The voltage parameter of the page buffer sensing signal is dynamically changed between two levels. The first voltage level is used during precharge to ensure reliable internal node charging, while the second voltage level is used during sensing to maximize sensing margin. This parameter change resolves the contradiction by applying different voltage conditions at different operational stages.
2Speed
If the sensing current is increased to improve sensing speed, then data retrieval becomes faster, but the voltage level stability deteriorates
Solution Approach 1:
The internal node is precharged to a stable voltage level before the sensing operation begins. This preliminary precharge action ensures that when sensing starts, the voltage baseline is stable, allowing for faster sensing current flow without compromising voltage stability during the actual sensing process.
Solution Approach 2:
The sensing signal voltage is switched to a second level that optimizes sensing speed while the precharged internal node maintains voltage stability. This periodic switching allows the system to achieve fast sensing without sacrificing voltage level stability, as the stability was established in the precharge phase.
3Device complexity
If a single voltage level is used for the page buffer sensing signal, then the circuit design is simplified, but the sensing reliability during different operation phases is compromised
Solution Approach 1:
The page buffer sensing signal transitions from a static single voltage level to a dynamic two-level system. The signal automatically switches between the first voltage level during precharge and the second voltage level during sensing, controlled by timing signals. This dynamic approach maintains sensing reliability across different operation phases while adding only minimal control complexity.
Data Source
AI summary
In an embodiment, a semiconductor memory device may include a memory cell array, a plurality of page buffers, and a control logic. The memory cell array may include a plurality of memory cells. The plurality of page buffers may be coupled to a plurality of bit lines of the memory cell array, respectively. The control logic may control the plurality of page buffers to perform a read operation on the memory cell array. Each of the plurality of page buffers may perform data sensing by changing a voltage of a page buffer sensing signal after an internal node is precharged.