Shared Redundant Memory Region for Cryogenic Repair
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Solution Overview
Problem
Memory devices operating at cryogenic temperatures face inefficiencies due to insufficient spare memory cells in some regions and excessive space usage in others, as well as the challenge of managing defective memory cells effectively.
Innovation Solution
A memory device design where multiple normal memory regions share a common redundant memory region, utilizing a repair circuit that shifts data lines based on addresses to replace defective cells with redundant ones, enhancing repair capabilities and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a spare memory region is allocated per memory region, then defective memory cells can be replaced within the corresponding allocated spare memory region, but when the number of defective memory cells exceeds the number of spare memory cells, the spare memory region does not have enough spare memory cells to replace all defective cells
Solution Approach 1:
The patent merges multiple separate spare memory regions into a single common spare memory region that serves multiple normal memory regions. This allows spare memory cells from different regions to be shared and reused, increasing the overall replacement capability without requiring each region to have its own dedicated spare cells.
Solution Approach 2:
The common spare memory region is designed to serve multiple normal memory regions simultaneously. The spare memory cells in this common region can be used to replace defective cells in any of the associated normal memory regions, providing universal replacement capability across multiple regions rather than being restricted to a single region.
2Reliability
If a larger spare memory region is allocated to hold more spare memory cells than there are memory cells in the corresponding memory region, then there are enough spare memory cells to replace all defective cells, but the spare memory region occupies an unnecessarily large area
Solution Approach 1:
By combining the spare memory regions of multiple normal memory regions into one common spare memory region, the patent achieves efficient utilization of spare memory cells. Instead of each region having its own oversized spare region, the shared common region is sized appropriately to serve all regions collectively, minimizing the total area occupied while ensuring sufficient replacement capability.
Solution Approach 2:
The patent changes the parameter of spare memory allocation from a per-region basis to a multi-region shared basis. This parameter change allows the spare memory region to be optimally sized based on the combined needs of multiple normal memory regions rather than being over-provisioned for each individual region.
3Loss of energy
If multiple normal memory regions share one redundant memory region, then spare memory allocation is optimized and power consumption is reduced, but the complexity of managing defective memory cells increases
Solution Approach 1:
The patent introduces a repair circuit as an intermediary component that manages the common spare memory region and handles the complexity of replacing defective cells across multiple normal memory regions. This repair circuit abstracts the management complexity, allowing the shared spare memory region to function efficiently while reducing power consumption through consolidated repair operations.
Data Source
AI summary
Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.