Mixed 1T and 2T Memory Cell Architecture for Row Hammer Mitigation
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Solution Overview
Problem
In memory devices, the access speed is limited by the time it takes to sense the small voltages produced by individual memory cells, and repeated accesses to certain memory cells can lead to increased memory degradation, particularly in 'row hammer' attacks, where nearby word lines experience elevated access rates.
Innovation Solution
Implementing a mixed memory cell architecture where counter memory cells use a 2T architecture for faster access and operation, while the rest of the memory cells along the word line use a 1T architecture, allowing for differential signal storage and enhanced access speed, and incorporating a refresh address control circuit to manage access counts and perform targeted refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all memory cells use 1T architecture, then device complexity is reduced, but access speed is limited by the time to sense small voltages from individual cells
Solution Approach 1:
The memory array is segmented into two distinct regions: a first region with 1T memory cells and a second region with 2T memory cells. This segmentation allows different portions of the memory to have different architectures optimized for their specific functions, enabling faster access in the 2T region without requiring the entire memory device to use the more complex 2T architecture.
Solution Approach 2:
Different regions of the memory array are assigned different qualities/architectures based on their functional requirements. The 2T memory cells in the second region provide enhanced access speed for specific operations (such as row hammer mitigation), while the 1T memory cells in the first region maintain simpler structure for general storage, allowing each local region to have the appropriate characteristics for its purpose.
2Productivity
If repeated accesses are made to certain memory cells, then access count increases, but memory degradation accelerates due to row hammer effects
Solution Approach 1:
The system performs preliminary actions by periodically refreshing memory cells based on accessed count thresholds before degradation occurs. The refresh address control circuit monitors access counts and proactively refreshes affected word lines before the row hammer effect can cause significant damage, preventing rather than reacting to the problem.
Solution Approach 2:
The refresh address control circuit implements a feedback mechanism by monitoring access counts of word lines and using this information to determine which word lines require refreshing. The circuit receives access count information, compares it against thresholds, and generates refresh addresses for word lines that have been accessed excessively, creating a closed-loop system that adapts to actual usage patterns.
Data Source
AI summary
Apparatuses and methods for 1T and 2T memory cell architectures. A memory array includes a word line which has both 1T and 2T portions. In the 1T portion, each sense amplifier is coupled to one memory cell along the word line. In the 2T portion, sense amplifiers are coupled to more than one memory cell along the word line each. For example, each sense amplifier in the 2T portion may be coupled to two bit lines, each of which intersect a memory cell along the word line. In some embodiments, the 2T portion may store a count value which represents an access count to the word line.