Semiconductor Memory Data Coding for Voltage Drop Stabilization
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Solution Overview
Problem
Conventional semiconductor memory devices experience logic state variations in initial operations due to voltage drops caused by inductors, particularly when the power supply voltage is low, leading to incorrect output of data bits.
Innovation Solution
A semiconductor memory device with counters and a data coding unit that selectively applies different operation modes to minimize the number of data bits in the first logic state and equalize the difference between data bits and flag information data bits in both logic states, thereby stabilizing the initial logic state of data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If data bits are output in the first logic state during initial operation, then the driving current of transmission stage TX is 20 mA, but the voltage drop due to the inductor becomes problematic when the power supply voltage VDD is low
Solution Approach 1:
The patent applies preliminary action by pre-coding the initial data before transmission. The data coding unit encodes the initial data to be transmitted such that the number of data bits in the first logic state is minimized. This preliminary encoding prevents the voltage drop problem from occurring in the first place, rather than trying to compensate for it after the fact.
Solution Approach 2:
The patent changes the parameter of data encoding to minimize the number of data bits in the first logic state. By modifying the encoding scheme specifically for initial data transmission, the patent alters the electrical characteristics of the transmitted signal to reduce the voltage drop across the inductor, thereby ensuring reliable data transmission at low power supply voltages.
2Reliability
If the voltage drop due to the inductor is large, then data bits that must be output in the first logic state may be output in a second logic state, but this causes the logic state of initial data to be varied
Solution Approach 1:
The data coding unit performs preliminary encoding of the initial data to minimize the number of data bits in the first logic state. This advance preparation ensures that when data is transmitted during initial operation, the voltage drop does not cause logic state variations, thereby maintaining both reliability and stability.
Solution Approach 2:
The patent implements a feedback mechanism where the data coding unit receives control signals based on the operation state of the memory device. During initial operation, the control signal indicates that data should be encoded to minimize first logic state bits. This feedback-based control ensures that the encoding strategy adapts to the operational context, preventing logic state variations.
3Reliability
If counters and data coding unit are added to minimize the number of data bits in the first logic state, then the voltage drop problem is solved, but the device complexity increases
Solution Approach 1:
The patent segments the data transmission process into different modes: initial operation mode and normal operation mode. The data coding unit is configured to apply different encoding strategies depending on the operation state. This segmentation allows the complex encoding function to be activated only when needed (during initial operation), reducing the overall impact on device complexity while maintaining reliability.
Solution Approach 2:
The data coding unit is designed to dynamically adjust its encoding behavior based on the operation state of the memory device. A control signal indicates whether the device is in initial operation or normal operation, and the coding unit adapts its encoding strategy accordingly. This dynamic approach allows the system to use complex encoding only when necessary, balancing reliability improvement with device complexity management.
Data Source
AI summary
A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.