STT-MRAM Write-Back Circuit for Data Integrity
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Solution Overview
Problem
Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) faces data integrity issues due to the potential for read operations to disturb the stored data, as the read current can approach or exceed the write current threshold, leading to invalid writes and data degradation.
Innovation Solution
Implementing a destructive write-back technique where data read from each memory cell is subsequently written back to that cell, ensuring data integrity by adding a write operation to the read cycle, which allows for accurate data preservation even if an invalid write occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read current is increased to improve read speed and accuracy, then read operation performance is improved, but data integrity deteriorates due to potential disturbance of stored data
Solution Approach 1:
The patent applies preliminary action by performing a write operation immediately after reading data from the memory cell. The read value is captured and then written back to the same cell, ensuring that any potential disturbance caused by the read current is corrected before the data is used. This preventive write-back operation restores the magnetic state of the free layer, thereby preserving data integrity while allowing higher read currents to be used for improved read performance.
2Measurement precision
If read current is increased to improve read accuracy, then measurement precision is improved, but harmful effects increase due to invalid writes and data degradation
Solution Approach 1:
The patent converts the harmful effect of read current-induced data disturbance into a beneficial process. By intentionally allowing the read operation to potentially disturb the data and then systematically correcting it through a write-back operation, the system ensures data integrity. The write-back operation acts as a corrective mechanism that transforms the potential harm of high read current into an opportunity to verify and restore data accuracy, thereby enabling higher read currents to be used safely for improved measurement precision.
3Reliability
If write operation is added to read cycle to preserve data integrity, then data integrity is improved, but operation time increases
Solution Approach 1:
The patent merges the read and write operations into a single integrated read cycle. The read operation and subsequent write-back operation are combined into one atomic process, where the read value is captured, processed, and written back without requiring separate operation sequences. This merging approach minimizes the overhead of the additional write operation by efficiently reusing the same circuit paths and control logic, thereby reducing the overall time penalty while ensuring data integrity is maintained throughout the combined operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains data integrity by incorporating an additional write operation in the read cycle, enabling STT-MRAM to operate at higher read voltages and providing more accurate read values while reducing the risk of data disturbance.
Implementation Method 1
Due to the tunnel magnetoresistive effect, the electrical resistance of the MTJ 100 changes based on the orientation of the polarities in the two magnetic layers
Implementation Method 2
During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer
Data Source
AI summary
Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation.