Semiconductor Memory Data Pin Termination for Parallel Testing
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Solution Overview
Problem
Conventional semiconductor memory devices require a large number of data channels for testing, which increases testing time and costs, necessitating a method to reduce the number of channels needed for efficient testing.
Innovation Solution
The semiconductor memory device employs a pin selection signal to enable or disable data pins, using termination resistors in input/output buffers to reduce the number of data channels required during testing, allowing multiple chips to be tested simultaneously by connecting data pins in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data pins are connected in parallel to test multiple chips simultaneously, then test efficiency is improved, but signal integrity and impedance matching deteriorate
Solution Approach 1:
The patent dynamically changes the impedance parameters of data pins by controlling termination resistors. During test mode, termination resistors are disabled to allow parallel connection for high productivity. During normal operation, termination resistors are enabled to maintain proper impedance matching and signal integrity. This parameter change resolves the contradiction between test efficiency and signal integrity.
Solution Approach 2:
The patent implements dynamic switching of data pin configurations between test mode and normal operation mode. A mode selection signal controls whether termination resistors are activated, allowing the system to adapt its electrical characteristics based on operational requirements. This dynamic adjustment enables both efficient parallel testing and reliable normal operation.
2Reliability
If termination resistors are enabled during test mode, then impedance matching is improved, but the ability to parallel connect data pins deteriorates
Solution Approach 1:
The patent uses a mode selection signal to dynamically control the state of termination resistors. In test mode, the signal disables termination resistors to enable parallel data pin connections. In normal operation mode, the signal enables termination resistors for proper impedance matching. This dynamic control resolves the contradiction between impedance matching and parallel testing capability.
Solution Approach 2:
The patent segments the operational modes into distinct test mode and normal operation mode, with different termination resistor configurations for each. This segmentation allows optimization for each specific mode without compromising the other, enabling both good impedance matching during normal operation and parallel testing capability during test mode.
3Ease of operation
If all data pins are enabled simultaneously, then normal data input/output operation is improved, but test capability for multiple chips deteriorates
Solution Approach 1:
The patent implements dynamic control of data pin enablement based on operational mode. During normal operation, all data pins are enabled for full data input/output capability. During test mode, only selected data pins are enabled while others are disabled and connected in parallel. This dynamic control resolves the contradiction between normal data operation and multi-chip test capability.
Solution Approach 2:
The patent applies different enablement states to different data pins based on local requirements. During test mode, some data pins are enabled for testing while others are disabled and repurposed for parallel connections. This local differentiation allows the system to optimize for multi-chip testing without completely sacrificing normal data operation capabilities.
Data Source
AI summary
A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled.