Synchronous DQS Input Buffer Control Using State Machine
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Solution Overview
Problem
Truncated input buffer disable periods in memory devices can cause partial reset of the DQS clock generator, leading to memory failures where data bits are dropped during write operations due to asynchronous behavior of the input buffer enable circuitry.
Innovation Solution
Implementing a synchronous solution for enabling and disabling data and DQS input buffers using an existing read-modify-write (RMW) state machine, which generates a synchronous DQS input buffer enable envelope with a CWL-shifter clock to ensure deterministic behavior and sufficient reset pulse durations without generating additional clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the input buffer is disabled to save power during separation between write commands, then power consumption is reduced, but the DQS clock generator may not properly reset leading to data bit drops
Solution Approach 1:
The patent applies preliminary action by ensuring the DQS clock generator is properly reset and synchronized before the input buffer is disabled. The state machine extends the input buffer disable period and ensures proper synchronization of the DQS clock generator before power-saving mode begins, preventing partial reset conditions that would cause data bit drops.
Solution Approach 2:
The patent implements feedback through a state machine that monitors the synchronization status of the DQS clock generator. The state machine tracks whether the clock generator has properly reset before allowing the input buffer to be disabled, and can extend the disable period if synchronization is not achieved, ensuring reliable operation before entering power-saving mode.
2Productivity
If the input buffer disable period is shortened to increase productivity, then write command throughput is improved, but the DQS clock generator reset may be truncated causing memory failures
Solution Approach 1:
The patent applies dynamics by making the input buffer disable period variable rather than fixed. The state machine dynamically adjusts the disable period length based on the actual synchronization status of the DQS clock generator, extending it when needed to ensure proper reset while minimizing it to maintain high throughput when conditions permit.
Solution Approach 2:
The state machine performs preliminary verification of DQS clock generator synchronization before allowing the input buffer disable period to begin. This ensures that the clock generator is properly reset in advance, preventing truncation issues even when the disable period is minimized for high throughput operation.
3Device complexity
If asynchronous input buffer enable circuitry is used to simplify control logic, then device complexity is reduced, but deterministic behavior cannot be achieved leading to sliver fails
Solution Approach 1:
The patent introduces a state machine as an intermediary between the asynchronous input buffer enable circuitry and the DQS clock generator. This state machine mediates the control signals, adding the necessary synchronization and timing control to achieve deterministic behavior while keeping the underlying asynchronous circuitry simple.
Solution Approach 2:
The patent replaces direct asynchronous electrical control with a state machine-based sequential control system. This substitution introduces deterministic timing and synchronization through the state machine's clocked operation, eliminating the unpredictable behavior of purely asynchronous control while maintaining relatively simple overall architecture.
Data Source
AI summary
A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.