Self-Adjusting Capacitive Coupling for Memory Voltage Boost
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Solution Overview
Problem
In single rail memory structures like SRAM, reducing the power supply voltage (Vdd) decreases power consumption and leakage but increases susceptibility to read and write failures, and existing voltage boosting techniques with fixed coupling capacitance are insufficient for long wordlines and cell supply lines, leading to performance issues.
Innovation Solution
The implementation of self-adjusting capacitive coupling-based voltage boosting, where wordlines and cell supply lines are positioned between voltage boost lines, allowing for dynamic voltage boosting during read and write operations by varying the charging of voltage boost lines based on the number of memory cells, thereby adapting the coupling capacitance to ensure effective voltage boost across the entire length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the power supply voltage (Vdd) is reduced to decrease power consumption and leakage, then power efficiency is improved, but the memory structure becomes more susceptible to read and write failures
Solution Approach 1:
The voltage boost lines are pre-charged to a voltage higher than Vdd before read or write operations. This preliminary charging creates coupling capacitance that automatically boosts the wordline voltage when activated, ensuring sufficient voltage margin for reliable operation even when Vdd is reduced for lower power consumption.
Solution Approach 2:
The voltage boost lines act as intermediary elements between the power supply and the wordline. By positioning these lines adjacent to the wordline and utilizing capacitive coupling, they transfer additional voltage energy to the wordline during operations, mediating the voltage deficiency that would otherwise occur at reduced Vdd levels.
2Power
If fixed coupling capacitance voltage boosting is used, then voltage boost is achieved, but it is insufficient for long wordlines and cell supply lines
Solution Approach 1:
The coupling capacitance is made dynamic by extending the voltage boost lines along the entire length of the wordline. This creates distributed coupling capacitance that adapts to the wordline length, providing sufficient voltage boost regardless of whether the wordline is short or long, unlike fixed capacitance approaches that fail for extended lengths.
Solution Approach 2:
The voltage boosting function is segmented along the wordline length by extending multiple voltage boost lines adjacent to different segments of the wordline. This distributed segmentation ensures that each portion of the long wordline receives adequate capacitive coupling and voltage boost, preventing voltage degradation along the length.
3Quantity of substance
If the number of memory cells in each row increases, then memory capacity is improved, but the length of wordlines and cell supply lines increases, requiring higher coupling capacitance
Solution Approach 1:
As memory capacity increases and wordline lengthens, the extended voltage boost lines automatically provide proportionally increased coupling capacitance. The capacitive coupling strength scales with the length of adjacent conductors, so longer wordlines in high-capacity memories receive greater voltage boost without additional design intervention.
Solution Approach 2:
The solution moves from considering only the horizontal wordline dimension to incorporating the vertical dimension by extending voltage boost lines adjacent to the wordline. This creates a two-dimensional capacitive coupling structure where the vertical extent of the boost lines provides the additional coupling needed for longer horizontal wordlines in high-capacity arrays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of read and write operations by ensuring consistent voltage boost across longer wordlines and cell supply lines, reducing the risk of failures and maintaining performance without increasing complexity or size, even as the number of memory cells increases.
Implementation Method 1
capacitive coupling-based voltage boosting
Data Source
AI summary
Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.