ReRAM Bit Line Voltage Control for Interconnection Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistance varying memory devices face challenges with voltage drop due to interconnection resistance, limiting read and reset margins and the number of bits that can be accessed simultaneously, especially during reset operations which require large currents.
Innovation Solution
A nonvolatile semiconductor memory device with a memory cell array configured as a matrix of ReRAM cells, using a bit line clamp circuit and a bit line voltage control circuit to detect and adjust the current flowing through the bit lines, compensating for voltage drops caused by interconnection resistance, thereby improving read and reset margins and enabling simultaneous access to more memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If resistance varying memory is used with Schottky diode and variable resistance element in series circuit, then memory cells can be easily stacked to three-dimensional structure for greater miniaturization, but relatively large current flows through interconnection lines during reset and read operations causing unignorable voltage drop
Solution Approach 1:
A voltage control circuit is introduced as an intermediary component between the memory cell array and the bit lines. This circuit detects the current flowing through bit lines and adjusts bit line voltages in real-time to compensate for voltage drops caused by interconnection resistance, thereby maintaining reliable read and reset margins while preserving the miniaturized three-dimensional memory structure
Solution Approach 2:
The voltage control circuit implements a feedback mechanism by continuously monitoring the current flowing through bit lines during reset and read operations. Based on this current information, the circuit dynamically adjusts the bit line voltages to compensate for voltage drops, ensuring that the voltage reaching the memory cells remains within the required margins for reliable operation
2Productivity
If large current flows through interconnection lines during reset operation to change resistance state, then reset operation can be performed, but voltage drop due to interconnection resistance reduces read margin and reset margin
Solution Approach 1:
The voltage control circuit serves as a mediator that decouples the relationship between high reset current and voltage margin degradation. By actively adjusting bit line voltages based on detected current levels, the circuit ensures that even during high-current reset operations, the voltage at the memory cell level remains sufficient to maintain required margins
Solution Approach 2:
The system dynamically changes the bit line voltage parameter based on the detected current flow. During reset operations with high current, the voltage control circuit increases bit line voltages to compensate for the larger voltage drops, thereby maintaining the voltage margin needed for reliable operation while allowing high-current reset to proceed
3Reliability
If voltage control circuit detects current and adjusts bit line voltage to compensate for voltage drop, then read margin and reset margin are improved, but device complexity increases
Solution Approach 1:
The voltage control circuit is designed to serve multiple functions: it detects current flowing through bit lines, determines voltage drop amounts based on detected current, and adjusts bit line voltages accordingly. This multi-functionality consolidates what could be separate complex circuits into a single integrated unit, reducing overall device complexity while maintaining improved read and reset margins
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.