DRAM Page Area Selective Enable for Power Reduction
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Solution Overview
Problem
Conventional DRAMs experience excessive power consumption due to enabling an entire page regardless of the size of data being accessed, leading to inefficient memory access operations.
Innovation Solution
A dynamic random access memory (DRAM) architecture that selectively enables only the necessary page areas based on the most significant bits (MSB) of the column address, using a row decoder and a column decoder to latch and decode addresses, and a method that involves generating a page area select signal to locally enable specific regions of the memory cell array, reducing unnecessary power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one page is enabled regardless of data size, then the memory cell array can be accessed efficiently, but power consumption increases excessively
Solution Approach 1:
The patent divides the memory cell array into multiple page areas (first page area and second page area) based on the column address. Instead of enabling the entire page, only the specific page area corresponding to the accessed data is enabled. This segmentation allows selective activation of memory regions, reducing unnecessary power consumption while maintaining access efficiency.
Solution Approach 2:
The patent applies local quality by enabling only the specific page area where data access is required, rather than uniformly enabling the entire page. The enabler circuit selectively activates either the first or second page area based on the column address, ensuring that power is consumed only in the locally required region.
2Ease of operation
If the entire page is enabled, then data access is simplified, but unnecessary memory cells consume power
Solution Approach 1:
The memory cell array is segmented into multiple page areas, and the enabler circuit selectively activates only the relevant segment based on the column address. This maintains ease of operation through automatic selection while preventing energy loss in inactive segments.
Solution Approach 2:
Instead of enabling the entire page (excessive action), the patent enables only the partial page area that is actually needed for data access. This partial action reduces energy consumption while still achieving the required data access function.
Data Source
AI summary
A dynamic random access memory includes: an address latch configured to latch a row address in response to a row address strobe (RAS) signal and latch a column address in response to a column address strobe (CAS) signal; a row decoder configured to decode the row address; an enabler configured to decode a part of most significant bits (MSB) of the column address to locally enable a part of one page area corresponding to the row address; and a column decoder configured to decode the column address.