Shaped Data in Resistive Memory for Leakage Current Control
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Solution Overview
Problem
Resistance-based random access memory devices face reliability issues in data storage and retrieval due to leakage current variability in their resistive network topology during read and write operations.
Innovation Solution
A data storage device is configured to store shaped data in resistance-based random access memory, controlling leakage current by adjusting the resistance states of neighboring storage elements, thereby reducing leakage current variability and mitigating its effects during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional erase operations are performed in resistance-based memory, then storage capacity is maintained, but leakage current variability increases and reliability deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between selected storage elements (subject to leakage current control) and unselected storage elements (maintained in high resistance state). This selective approach reduces overall leakage current variability by controlling only the necessary elements while preserving the high resistance state of others, thereby improving reliability without sacrificing storage capacity.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting resistance states of storage elements based on selection status. Selected elements are programmed to specific resistance states (low or high) based on data values, while unselected elements are maintained in high resistance state. This parameter control mechanism reduces leakage current variability and improves data storage reliability.
2Reliability
If leakage current is controlled by adjusting neighboring storage elements, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-charging bit lines to a first voltage level before read operations. This preliminary charging ensures that selected storage elements in high resistance state do not cause excessive voltage drops or leakage current variability during reading, thereby improving reliability without requiring complex real-time control mechanisms.
Solution Approach 2:
The patent uses sense amplifiers as intermediaries to detect and compensate for leakage current effects. The sense amplifiers measure the actual current through selected storage elements and provide feedback for correction, thereby managing leakage current variability through a dedicated intermediary component rather than complexifying the entire control system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively controls leakage current variability, allowing for predictable and expected ranges during read and write operations, reducing the need for estimating specific leakage current values and improving data storage reliability.
Implementation Method 1
Resistance-based random access memory devices use a variable resistive material to store data. The variable resistive material has a resistance that can be changed responsive to a programming voltage.
Implementation Method 2
A sense amplifier coupled to the first bit line may sense current (e.g., a 'read current') that flows through the first bit line. The current flowing through the first bit line is responsive to the voltage across the first storage element. Thus, the current can be used to determine a resistance state of the first storage element using Ohm's law.
Data Source
AI summary
A method includes, in a data storage device including a resistive memory, receiving, from an external device, an erase command to erase a portion of the resistive memory. The method further includes storing shaped data at the portion of the resistive memory responsive to the erase command. Shaped data is configured to control an amount of leakage current during a read and/or write operation at one or more storage elements that are adjacent to at least one storage element of the portion of the resistive memory.