Multi-port Memory Clock Generator Frequency Adaptation

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Solution Overview

Problem

Conventional multi-port memory devices face limitations in operating at various frequencies, often requiring multiple pins for different clock signals, which restricts their adaptability and increases pin count.

Innovation Solution

Incorporating a clock generator that produces internal clock signals with varying frequencies, and local clock generators within each port to adjust these frequencies based on an external clock signal, allowing each port to operate optimally without increasing the number of pins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple external clock signals with different frequencies are received through separate pins, then each port can operate at its required frequency, but the number of pins increases

Engineering Contradiction:
Improvefrequency adaptabilityVSAvoidpin count
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A single external clock signal pin serves multiple ports by providing a common clock source that is internally divided into different frequencies. The clock generator unit receives one external clock signal and generates multiple internal clock signals with different frequencies, allowing each port to operate at its required frequency without requiring separate external clock pins.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The clock generator unit acts as an intermediary between the external clock signal and the multiple ports. It receives the single external clock signal and transforms it into multiple internal clock signals with different frequencies, mediating the frequency distribution to each port according to their specific requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If all ports operate with the same internal clock signal, then pin count is reduced, but adaptability to different frequency requirements is limited

Engineering Contradiction:
Improvepin countVSAvoidfrequency adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The clock generator unit segments the single external clock signal into multiple internal clock signals with different frequencies. Each port receives a segmented clock signal appropriate to its frequency requirements, allowing differentiated operation while maintaining a unified external interface.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The clock generator unit changes the frequency parameter of the clock signal by generating multiple internal clock signals with different frequencies from a single external clock source. This allows each port to operate at its optimal frequency while using the same external clock pin.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If each port has independent frequency control, then frequency precision is improved, but device complexity increases

Engineering Contradiction:
Improvefrequency precisionVSAvoidcontrol structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The clock generator unit merges the frequency control function for all ports into a single centralized unit. Instead of each port having independent frequency control circuitry, the clock generator unit consolidates the frequency division and distribution function, reducing overall device complexity while maintaining precise frequency control for each port.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7369453B2Multi-port memory device and method of controlling the same
Publication Date: 2008.05.06 SAMSUNG ELECTRONICS CO LTD
  • US7369453B2 patent drawing
  • US7369453B2 patent drawing
  • US7369453B2 patent drawing

AI summary

A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.