DDR2 SDRAM Common-Mode Signal Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DDR2 memory circuits face challenges in optimizing logic functions while minimizing circuit area to enhance performance, with increased latency and power consumption being trade-offs for faster throughput.
Innovation Solution
A DDR2 memory circuit design featuring a low-speed input path and a high-speed input path coupled by an input coupling, forming a common input to a memory core with both paths coupled together, allowing for varying common-mode voltage to transmit logical signals, reducing the need for separate input and output paths and package pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate input paths and output paths are used for high-speed and low-speed signals, then signal transmission reliability is improved, but device complexity and packaging requirements increase
Solution Approach 1:
The patent merges high-speed and low-speed signal paths into a single common input path and common output path. The high-speed differential data signals and low-speed control signals share the same physical routing from the memory core to external interfaces, eliminating the need for separate paths and reducing overall circuit area while maintaining signal transmission reliability through proper signal conditioning and timing control
Solution Approach 2:
The common input and output paths serve multiple functions by carrying both high-speed differential data signals and low-speed control signals. This multi-functional approach allows the same physical infrastructure to handle different signal types with different speed requirements, thereby reducing device complexity and packaging requirements without sacrificing the reliability needed for high-speed operation
2Adaptability or versatility
If more wires are added to support additional functions like error reporting, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements error reporting and additional control functions by utilizing the existing common input and output paths that already carry high-speed and low-speed signals. The same physical infrastructure supports both data transmission and error reporting capabilities, allowing the system to gain adaptability without adding separate dedicated wires for error handling functions
3Productivity
If common-mode voltage is varied to transmit logical signals, then data transmission efficiency is improved, but control signal generation complexity increases
Solution Approach 1:
The patent varies the common-mode voltage level as a parameter to encode logical signals transmitted over the common input and output paths. By changing the common-mode voltage between different states, the system efficiently transmits both high-speed differential data and low-speed control signals through the same infrastructure, improving data transmission efficiency without requiring completely separate control signal generation paths
Data Source
AI summary
A double-data-rate two synchronous dynamic random access (DDR2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.