SRAM Bitcell Isolator Noise Margin
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Solution Overview
Problem
Existing memory bitcells face challenges in retaining data at ultra-low supply voltages and maintaining low read energy, which is crucial for energy-harvested sensor nodes like solar cell-powered devices, as they are prone to noise-induced state flips, leading to data loss.
Innovation Solution
A storage bitcell design featuring cross-coupled inverters with strategically placed isolators between the inverters and potential rails, which increases the noise margin during read and retention modes by isolating the inverters from noise sources, ensuring data stability at low voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolators are added to increase noise margin, then data stability is improved, but device complexity increases
Solution Approach 1:
Isolator transistors are introduced as intermediary elements between the storage node and potential rails. These isolators act as mediators that conditionally connect or disconnect the storage node from noise sources, thereby improving data stability without permanently increasing circuit complexity. The isolators are controlled to be active only when needed for noise protection.
Solution Approach 2:
The isolators are designed to dynamically adjust their connection state based on operating conditions. During retention modes, the isolators connect to provide noise protection. During read/write operations, the isolators disconnect to allow proper signal propagation. This dynamic behavior allows the circuit to maintain low complexity while achieving high reliability when needed.
2Reliability
If isolators are used to protect from noise, then noise margin is improved, but read energy increases
Solution Approach 1:
The isolators are activated periodically and selectively based on the operational phase. During read operations, the isolators are temporarily deactivated to minimize energy consumption, and only activated during retention phases when noise protection is required. This periodic activation strategy reduces overall read energy while maintaining noise margin when needed.
Solution Approach 2:
The isolators are strategically placed only at critical nodes where noise protection is most needed, rather than uniformly across the entire circuit. This localized approach provides effective noise margin improvement at the most vulnerable points while minimizing the total number of isolators and their associated energy consumption during read operations.
3Use of energy by moving object
If operating voltage is reduced for energy efficiency, then power usage is improved, but noise immunity deteriorates
Solution Approach 1:
The isolators serve as intermediary protective elements that enable ultra-low voltage operation by blocking noise paths. At ultra-low supply voltages (e.g., 0.45V), the reduced signal margins make the circuit more susceptible to noise, but the isolators prevent noise coupling, thereby maintaining noise immunity despite the reduced operating voltage and improved power efficiency.
Solution Approach 2:
The isolators provide preliminary protection against noise before it can affect the storage node during ultra-low voltage operation. By preemptively blocking noise paths through the isolators, the circuit maintains stability even at reduced voltages where the inherent noise margin would otherwise be insufficient, thus enabling energy-efficient operation without sacrificing reliability.
Data Source
AI summary
A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.