Memory Device Failure Detection via Floating Sub-Wordline Decoders
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Solution Overview
Problem
As memory devices experience increased integration density, internal potential failures in memory cells, wordlines, and bitlines become more prevalent, making it challenging to effectively detect and address these failures to maintain device quality.
Innovation Solution
The implementation of a memory device design that includes a memory cell array connected to wordlines and bitlines, a wordline driving circuit with sub-wordline decoders, and a logic circuit that controls power supply voltages and driving signals to detect failures by floating unselected sub-wordline decoders and using sense amplifiers to read data from unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density of memory devices is increased, then storage capacity is improved, but internal potential failures in memory cells, wordlines, and bitlines increase
Solution Approach 1:
The patent applies preliminary action by performing failure detection before the failures actually affect normal operation. The logic circuit proactively tests wordlines by floating unselected sub-wordline decoders and using sense amplifiers to detect potential failures in unselected memory cells, allowing the system to identify and address issues before they cause data corruption or device failure during regular operation.
2Stability of the object's composition
If sub-wordline decoders are kept connected to power supply voltage, then operational stability is improved, but potential failures in unselected wordlines cannot be detected
Solution Approach 1:
The patent applies dynamics by making the power supply connection to sub-wordline decoders dynamic rather than static. The logic circuit selectively controls the connection state of each sub-wordline decoder to the power supply voltage based on whether it is selected or unselected. During failure detection, unselected sub-wordline decoders are disconnected from the power supply to enable floating and subsequent failure detection, while maintaining operational stability during normal operation when all decoders remain connected.
3Difficulty of detecting and measuring
If unselected wordlines are floated to detect failures, then failure detection capability is improved, but operational continuity is disrupted
Solution Approach 1:
The patent applies periodic action by implementing failure detection as a periodic or on-demand operation rather than a continuous process. The logic circuit periodically performs failure detection by floating unselected wordlines and using sense amplifiers to read memory cell data, while maintaining normal operational continuity during non-detection periods. This allows the system to balance failure detection capability with operational productivity by conducting tests at appropriate intervals or when specifically triggered.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders respectively connected to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and wherein each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected, The memory device may include a sense amplifier circuit including sense amplifiers connected to the bitlines, and a logic circuit configured to determine a failure of at least one of the memory cell array and the wordline driving circuit.