Stacked Memory Decoder Layer Alternation
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Solution Overview
Problem
The challenge in semiconductor technology is to enhance the integration density and data processing capacity of multilayer memory devices, as existing circuits are difficult to arrange and restrict increases in integration density.
Innovation Solution
A stacked memory device design featuring alternately disposed X-decoder and Y-decoder layers between memory groups, with each decoder layer connected to neighboring memory groups, allowing for efficient decoding of address information and reducing complexity and integration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilayer memory devices are stacked to increase integration density, then memory capacity is improved, but circuit arrangement difficulty increases and integration becomes more complex
Solution Approach 1:
The decoder circuits are segmented into X-decoder layers and Y-decoder layers that are alternately disposed between memory groups. Each decoder layer is further divided into multiple decoder blocks that can be independently arranged. This segmentation allows the complex decoding function to be distributed across multiple simpler components, making circuit arrangement more manageable while supporting increased memory capacity through additional stacking layers.
Solution Approach 2:
The patent transitions from planar circuit arrangement to three-dimensional stacking by disposing decoder layers alternately between memory groups in the vertical direction. This dimensional change allows circuits to be arranged in the depth direction rather than only in the plane, significantly increasing integration density and memory capacity while maintaining manageable circuit complexity through systematic layering.
2Quantity of substance
If more memory layers are stacked to increase integration density, then memory capacity is improved, but decoder circuit arrangement becomes more difficult
Solution Approach 1:
Decoder circuits are divided into X-decoder layers and Y-decoder layers, with each layer containing multiple decoder blocks. This segmentation creates modular units that can be systematically manufactured and assembled, making it easier to handle increased integration density through standardized repetitive structures rather than complex custom arrangements.
Solution Approach 2:
By arranging decoder layers in the vertical dimension between memory groups rather than expanding horizontally, the patent enables increased integration density without proportionally increasing manufacturing complexity. The alternating pattern creates a regular three-dimensional structure that simplifies manufacturing processes compared to dense planar arrangements.
3Productivity
If decoder layers are disposed between memory groups to improve connection efficiency, then data processing capability is improved, but device structure becomes more complex
Solution Approach 1:
The decoding function is segmented into separate X-decoder and Y-decoder layers disposed between memory groups, allowing each decoder type to be optimized independently for its specific function. This segmentation improves data processing capability by enabling parallel operation of X and Y decoders while managing structural complexity through functional separation.
Solution Approach 2:
The alternately disposed X and Y decoder layers serve multiple functions: they decode address information for their respective memory groups, provide structural organization for the stacked device, and enable parallel data processing operations. This multi-functionality improves productivity while containing device complexity through unified structural design.
Data Source
AI summary
A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.