Fast Cyclic Decoder Circuit for FIFO Buffer Wordline Delay
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Solution Overview
Problem
Prior-art decoder circuits for FIFO and LIFO buffers do not optimize the decoding process, leading to increased delay in wordline generation due to the large number of AND/NAND gates required, which is directly related to the number of bits to be decoded.
Innovation Solution
The implementation of a fast decoder system using a clock generator, monotonic and static flip-flops, and combinational logic to efficiently generate new wordlines by capturing changed bits and old wordlines, reducing the delay by utilizing a smaller number of two-input AND gates and Gray coding for address changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a generalized N to 2N decoder is used to decode pointers in any order, then the decoder can handle any access pattern, but the delay in wordline generation increases due to the larger number of AND/NAND gates required
Solution Approach 1:
The decoder is segmented into two functional parts: a monotonic decoder that handles the predictable sequential portion of address decoding, and a generalized decoder that handles the remaining non-sequential addressing. This segmentation allows the majority of decoding to occur through simple sequential logic rather than complex combinatorial logic, reducing overall delay while maintaining full decoding capability.
Solution Approach 2:
The monotonic decoder performs preliminary decoding of the most significant bits that follow a predictable sequential pattern. By pre-decoding these bits before the generalized decoder processes the remaining bits, the system reduces the critical path delay through the decoder chain while maintaining the ability to handle any access pattern.
2Area of stationary object
If the number of bits to be decoded is increased, then the decoder can address larger memory spaces, but the delay increases due to the larger number of AND/NAND gates in the decoding path
Solution Approach 1:
The address decoding is segmented into monotonic bits (handled by the monotonic decoder) and non-monotonic bits (handled by the generalized decoder). This segmentation reduces the number of gates in the critical path while still supporting the full addressable memory space, as the monotonic portion uses simpler sequential logic.
Solution Approach 2:
The decoder architecture dynamically adapts to the addressing pattern by using the monotonic decoder for the predictable sequential portion of addresses and the generalized decoder for the remaining portions. This dynamic approach optimizes the decoding path based on the actual access pattern, reducing delay for sequential accesses while maintaining full addressing capability.
Data Source
AI summary
Embodiments of systems and methods for improved first-in-first-out (FIFO), last-in-last out (LIFO) and full-cycle decoders are described herein. In the various embodiments of the system, a clock generator is operable to generate a clock signal having an active phase and an inactive phase. A set of monotonic flip-flops are operable to capture a set of incoming data addresses during the active cycle of the clock and to generate therefrom data corresponding to single bits in the addresses that have changed compared to the data addresses received by the set of monotonic flip-flops during an immediately preceding data capture cycle. A set of static flip-flops are operable to capture a set of incoming data addresses during the inactive phase of the clock cycle and to generate set output data therefrom. A decoder operable to process the set output data from the set of static flip-flops and to generate a set of old wordlines corresponding to a set of data addresses in the immediately preceding data capture cycle. Combinational is logic operable to receive the set of single changed bits and the set of old wordlines and to generate therefrom a set of new wordlines. Methods are also described herein for using the aforementioned system.