Semiconductor Memory Test Data Output Mode Control
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in efficiently managing test data output during testing operations, lacking flexible and efficient methods to handle various output modes such as serial, parallel, and staggered modes.
Innovation Solution
Incorporating a training unit with a latch section, control signal generation part, and output circuit that generates and outputs test data in response to selection signals and mode control signals, allowing for flexible data output in different modes by selectively driving latches and amplifying data for output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a semiconductor memory apparatus performs test operations with multiple output modes (serial, parallel, staggered), then the versatility of testing capabilities is improved, but the device complexity increases due to the need for additional control circuits and latch structures
Solution Approach 1:
The output circuit is designed to perform multiple functions by supporting serial, parallel, and staggered output modes through a unified structure controlled by mode selection signals. The same output circuit hardware can operate in different modes based on control signals, eliminating the need for separate dedicated circuits for each mode and reducing overall device complexity while maintaining versatility
Solution Approach 2:
The latch section and output circuit are configured to dynamically switch between different output modes based on control signals. The latch address signal and data output mode selection signal enable dynamic reconfiguration of the test data output path, allowing the system to adapt its behavior without physical reconfiguration, thus managing complexity through software/control-signal-based flexibility
2Device complexity
If test data is output in serial mode, then the device complexity is reduced, but the productivity decreases due to increased latency and slower data output
Solution Approach 1:
The system dynamically selects between serial and parallel output modes based on testing requirements. The output circuit can switch from serial output (simpler control) to parallel output (faster data transfer) using mode selection signals, allowing the system to optimize for speed when needed without being permanently constrained to a slower mode, thus resolving the productivity-complexity tradeoff
3Quantity of substance
If multiple latches are used to store test data, then the quantity of stored test data is improved, but the device complexity increases due to additional latch control and selection circuits
Solution Approach 1:
The latch section uses a unified control structure that can manage multiple latches through a common control mechanism. The latch address signal and enable signals are generated by a single control circuit that can selectively activate different latches based on the desired output mode, allowing multiple latches to be managed with a single control logic unit rather than requiring independent control circuits for each latch
Solution Approach 2:
The test data storage is divided into multiple latches that can be independently controlled and selected. By segmenting the storage into discrete latch units with common control signals, the system achieves increased data capacity while managing complexity through modular architecture where each latch is a standardized unit controlled by a central control mechanism
Data Source
AI summary
A semiconductor memory apparatus includes a latch section including a plurality of latches configured to store test data, a control signal generation part configured to generate a mode selection signal in response to a latch address signal and a first mode signal, and an output circuit configured to operate in accordance with a training enable signal, and generate at least a subset of test data output by each of the plurality of latches in response to a latch selection signal, the mode selection signal, and a second mode signal.