Memory Device Adjacent Line Biasing Leakage Control
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Solution Overview
Problem
In nonvolatile memory devices, leakage of program current to unselected memory cells reduces the sensing margin of selected memory cells, affecting the reliability and efficiency of read and write operations.
Innovation Solution
A memory device and method that control unselected memory cells by biasing adjacent word lines and bit lines to non-selection voltages and floating non-adjacent lines during access operations, minimizing leakage current and optimizing voltage levels for improved sensing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program current is applied to selected memory cell, then write operation is performed, but leakage current flows to unselected memory cells reducing sensing margin
Solution Approach 1:
The patent applies different voltage conditions to different groups of unselected memory cells based on their spatial relationship with the selected cell. Specifically, unselected cells connected to adjacent word lines or bit lines receive a first voltage (e.g., 0V or negative voltage) to suppress leakage current, while unselected cells connected to non-adjacent lines receive a second voltage (e.g., floating or ground potential). This localized differentiation of voltage application effectively reduces leakage current in the most problematic regions without unnecessarily affecting other cells, thereby improving sensing margin while minimizing energy loss.
2Loss of energy
If all unselected memory cells are biased to non-selection voltage, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent segments the unselected memory cells into distinct groups based on their connectivity: cells connected to adjacent word lines, cells connected to adjacent bit lines, and cells connected to non-adjacent lines. Each segment is then subjected to an appropriate voltage condition. This segmentation approach allows the system to apply complex voltage control only where necessary (to adjacent lines) while using simpler control for non-adjacent lines, thereby reducing overall device complexity compared to uniformly biasing all unselected cells.
3Reliability
If adjacent word lines and bit lines are biased to non-selection voltage, then leakage current to unselected cells is minimized, but power consumption increases
Solution Approach 1:
The patent applies partial action by selectively biasing only the adjacent word lines and bit lines to non-selection voltage, rather than biasing all unselected lines. This partial application of voltage control is sufficient to suppress the majority of leakage current paths that significantly impact sensing margin, while avoiding the excessive power consumption that would result from biasing all unselected lines. The approach achieves adequate leakage suppression with optimized power consumption.
Data Source
AI summary
A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.