Buried Bitline Semiconductor Device Reducing Parasitic Capacitance
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Solution Overview
Problem
Conventional trench gate type semiconductor devices face issues with high parasitic capacitance due to the use of silicon nitride films for dielectric layers, which affects the operation speed and production yield, and require complex processes for bitline formation and memory element contact plug placement.
Innovation Solution
The semiconductor device employs silicon oxide films for bitline spacers and cap dielectric layers, reducing parasitic capacitance and simplifying the bitline formation process, while also eliminating the need for a memory element contact plug by burying the bitline in a shallower area within the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If silicon nitride films are used for dielectric layers in trench gate type semiconductor devices, then the device structure can be formed, but high parasitic capacitance occurs which reduces operation speed and production yield
Solution Approach 1:
The patent changes the material parameter of the dielectric layer from silicon nitride to silicon oxide. This material substitution directly reduces the parasitic capacitance between the bitline and the substrate, thereby improving operation speed and production yield without compromising the structural integrity of the trench gate device.
2Ease of manufacture
If conventional trench gate type structures are used, then memory cells can be formed, but complex processes are required for bitline formation and memory element contact plug placement
Solution Approach 1:
The patent extracts and eliminates the memory element contact plug from the conventional structure. By burying the bitline in a shallower area within the substrate and using silicon oxide for bitline spacers, the need for separate contact plug formation processes is removed, significantly simplifying the manufacturing process while maintaining device functionality.
3Reliability
If bitlines are formed using conventional methods, then electrical connections can be established, but contact resistance is high and capacitor arrangement is less dense
Solution Approach 1:
The patent changes the vertical positioning (depth dimension) of the bitline within the substrate. By burying the bitline in a shallower area, the structure enables closer-packed capacitor arrangement in the horizontal plane while maintaining low contact resistance through optimized silicon oxide spacer formation, thus improving both reliability and area utilization.
Data Source
AI summary
There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.