Buried Capacitor Memory Cell Soft Error Protection

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Solution Overview

Problem

Reduced geometry integrated circuit memory chips are vulnerable to soft errors due to particle-induced charge fluctuations, which reduce reliability and are costly to mitigate with existing techniques that increase substrate surface area and complexity.

Innovation Solution

A semiconductor memory device with a bi-stable flip-flop cell featuring capacitors with a top conductive electrode overlying a bottom contact electrode and a dielectric layer, providing improved protection against soft errors by increasing capacitance per unit area without adding substrate layers or complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional techniques (Deep_Nwell, polyimide) are used to reduce soft errors, then soft error protection is improved, but substrate surface area increases and device complexity increases

Engineering Contradiction:

Improvesoft error protectionVSAvoidsubstrate layers and surface area

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the capacitor structure with the existing memory cell layout by forming the bottom contact electrode to overlay multiple active regions (both NFET and PFET transistors). This integration allows the capacitor to be embedded within the existing cell footprint rather than adding separate protective structures, thereby improving soft error protection through increased capacitance without increasing device complexity or substrate surface area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from planar capacitor structures to a vertical/dimensional approach by forming the bottom contact electrode that overlays multiple active regions in the vertical dimension. The capacitor extends through the substrate depth, utilizing the vertical space between metal layers rather than expanding horizontally, which protects against soft errors without increasing substrate surface area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If capacitor value per unit area is increased to reduce soft errors, then soft error rate is improved, but fabrication complexity and cost increase

Engineering Contradiction:

Improvesoft error rateVSAvoidfabrication complexity and cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The bottom contact electrode serves multiple functions: it acts as the bottom electrode for both the first and second capacitors simultaneously, and it overlays both NFET and PFET active regions. This multi-functionality allows a single fabrication step to create capacitors for multiple memory cells, increasing capacitance per unit area while simplifying the manufacturing process and reducing fabrication cost.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent changes the geometric parameters of the capacitor structure by forming the bottom contact electrode with dimensions and positioning that allow it to overlay multiple active regions. This parameter optimization increases the effective capacitance area without requiring additional fabrication steps, thereby improving soft error rate protection while maintaining ease of manufacture.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If reduced geometry and reduced operating voltage are used to increase chip density, then chip density and performance are improved, but vulnerability to particle-induced soft errors increases

Engineering Contradiction:

Improvechip density and performanceVSAvoidvulnerability to soft errors

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies local quality enhancement by forming the bottom contact electrode to specifically overlay the active regions of both NFET and PFET transistors where charge storage is critical. This localized approach concentrates the capacitance enhancement exactly where needed to protect against soft errors, allowing reduced geometry designs to maintain reliability without compromising chip density or performance.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces soft error rates while maintaining cost-effectiveness and compatibility with traditional memory cell substrate areas, enhancing the reliability and performance of memory chips.

Implementation Method 1

Each one of the first and second capacitors includes a top conductive electrode overlying a bottom contact electrode with a dielectric layer disposed in-between

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS7864561B2Cell structure with buried capacitor for soft error rate improvement

Publication Date: 2011.01.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor memory device with an improved protection against soft errors includes a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor electrically couples the data storage node to a predefined voltage and a second capacitor electrically couples the data bar storage node to the predefined voltage. Each one of the first and second capacitors includes a top conductive electrode overlying a bottom contact electrode with a dielectric layer disposed in-between. The bottom contact electrode overlays at least two different active regions forming the data and data bar storage nodes.