Buried-Chip Antenna Substrate Layout for mm-Wave Module Size Limits
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing frequency and bandwidth for mm-wave and 5G antenna modules, requiring reduced size and minimized interference, while maintaining geometric constraints and improving signal radiation efficiency.
Innovation Solution
A semiconductor device design featuring a substrate with buried semiconductor chips and stacked antenna patterns on both surfaces, reducing the size and improving electric characteristics by minimizing the length of electric connection paths and optimizing antenna placement to enhance signal radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the frequency and bandwidth of electromagnetic wave are increased for mm-wave and 5G antenna modules, then the performance of electronic devices is improved, but the size of the module increases and interference between parts occurs
Solution Approach 1:
The patent utilizes both top and bottom surfaces of the substrate to place antenna patterns, transitioning from a single-plane arrangement to a three-dimensional spatial distribution. This dimensional change allows multiple antenna patterns to be accommodated within the same footprint area, increasing frequency and bandwidth capabilities without proportionally increasing module size.
Solution Approach 2:
The patent embeds semiconductor chips within recesses formed in the substrate, creating a nested structure where chips are integrated into the substrate volume rather than occupying separate mounting space. This nesting approach reduces the overall module size while maintaining high-frequency performance.
2Power
If multiple antenna patterns are placed on the substrate, then signal radiation efficiency is improved, but shadow regions are created and interference between antenna patterns occurs
Solution Approach 1:
By distributing antenna patterns across both top and bottom surfaces of the substrate, the patent creates spatial separation between antenna elements. This three-dimensional arrangement reduces shadow regions cast by chips and other components, allowing multiple antenna patterns to operate at high frequencies without significant mutual interference.
Solution Approach 2:
The patent assigns different regions of the substrate (top surface, bottom surface, different zones) to specific antenna patterns based on their radiation characteristics and interference profiles. Each antenna pattern is optimally positioned in a location that maximizes its radiation efficiency while minimizing impact on other antenna elements.
3Reliability
If semiconductor chips are mounted on the surface of the substrate, then electrical connection is established, but the length of electric connection path increases and device size increases
Solution Approach 1:
The patent forms recesses in the substrate and embeds semiconductor chips within these recesses. This nesting structure positions the chips closer to the antenna patterns and reduces the distance that electrical signals must travel through connection paths, thereby reducing the overall length of electric connection paths while maintaining reliable electrical connection.
Solution Approach 2:
Instead of mounting chips on the external surface of the substrate, the patent inverts the conventional approach by embedding chips within the substrate volume. This inversion allows the chips to be surrounded by the substrate material, creating shorter and more direct electrical connection paths to antenna patterns on both surfaces.
Data Source
AI summary
A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.