Buried Drain Transistors for High Voltage Handling
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Solution Overview
Problem
High voltage operation in semiconductor devices, such as field effect transistors, often requires larger transistors and additional manufacturing processes, leading to increased device size and cost, as well as limitations in voltage thresholds that can result in reduced electrical and thermal robustness.
Innovation Solution
The implementation of a semiconductor device with a buried drain region and spacer doping region, which extends vertically into the substrate, allowing for an increased effective length of the drain region without increasing the lateral size, thereby enabling higher voltage handling while maintaining device compactness and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used to handle voltages greater than 5V, then the voltage handling capability is improved, but the device size increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar transistor structures to vertically stacked three-dimensional structures. Multiple transistor layers are stacked above each other, utilizing the vertical dimension to increase device density and functionality without expanding the lateral footprint. This enables high voltage handling capability while maintaining compact device size.
Solution Approach 2:
The patent implements nested structures where smaller functional components are integrated within or between larger structural elements. Transistor layers are stacked and interconnected in a nested configuration, with each layer containing complete transistor functionality. This nesting approach allows multiple high voltage transistors to be integrated in a compact volume, improving voltage handling while controlling device size.
2Reliability
If high voltage transistors are used to handle voltages greater than 5V, then the voltage handling capability is improved, but additional manufacturing processes are required
Solution Approach 1:
The patent employs preliminary formation of sacrificial structures (such as sacrificial layers or dummy structures) during the manufacturing process that are later removed. These preliminary structures facilitate the creation of complex stacked transistor architectures through standard processing steps. By preparing these structures in advance, the manufacturing process becomes more systematic and less complex, enabling high voltage transistor fabrication without requiring excessive additional process steps.
3Reliability
If transistor stacking is performed to fulfill 5V voltage requirements, then the voltage handling capability is improved, but additional circuits are required
Solution Approach 1:
The patent designs universal transistor structures that can operate in multiple voltage regimes. The stacked transistor architecture is configured so that the same physical structure can handle both low voltage and high voltage operations by appropriately biasing different layers. This multi-functionality eliminates the need for separate dedicated high voltage transistor circuits, reducing overall circuit complexity while maintaining 5V handling capability.
Data Source
AI summary
A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.