Buried Gate Access Transistor for Magnetic Memory Cell Density
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Solution Overview
Problem
Current magnetic memory cells are large due to the horizontal configuration of access transistors, limiting their efficiency and preventing them from replacing other memory types like DRAM and NAND flash, due to low drive current, punch-through leakage, and insufficient space for contact formation.
Innovation Solution
The access transistor is designed with a gate positioned substantially perpendicular to the silicon substrate, burying it and allowing additional surface area for more memory cells, reducing the size of the magnetic memory cell to 5F2 compared to prior art sizes of 12F2, and increasing the source-drain current by forming a dual channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the access transistor is formed horizontally beside and under the MTJ, then the transistor can be easily fabricated, but the memory cell size becomes large (14F2)
Solution Approach 1:
The gate of the access transistor is repositioned from a horizontal configuration to a vertical configuration, extending substantially perpendicular to the plane of the silicon substrate. This dimensional change allows the gate to occupy the third dimension (depth) rather than consuming horizontal surface area, thereby reducing the memory cell footprint from 14F2 to approximately 6F2 while maintaining ease of fabrication through standard vertical processing techniques
2Device complexity
If the gate is positioned horizontally, then the transistor structure is simple, but the surface area for additional memory cells is insufficient
Solution Approach 1:
The gate structure transitions from a planar horizontal layout to a vertical configuration that extends perpendicular to the silicon substrate surface. This allows the gate to utilize the depth dimension of the device, freeing up horizontal surface area for additional memory cells while maintaining a relatively simple transistor structure that can be integrated into existing fabrication processes
3Area of stationary object
If the memory cell size is reduced to increase density, then more cells can fit on the substrate, but drive current and contact space become insufficient
Solution Approach 1:
By positioning the gate vertically perpendicular to the substrate, the invention reduces the horizontal footprint of each memory cell, allowing higher cell density. The vertical gate configuration maintains adequate channel length for sufficient drive current while freeing up horizontal space for contact formation and interconnect routing, thus resolving the trade-off between size reduction and electrical performance
Data Source
AI summary
A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.