Buried Gate Semiconductor Device Contact Alignment
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Solution Overview
Problem
The increasing integration of semiconductor devices leads to reduced contact sizes and aspect ratios, causing challenges in contact formation and resulting in Self Align Contact (SAC) failures and increased production yield issues, particularly with buried gate structures.
Innovation Solution
A method for forming a semiconductor device with a buried gate that involves forming an insulating layer on the substrate, selectively removing it to expose the active region, and creating a storage electrode contact plug with an extended lower part to prevent oxidation and improve alignment, thereby reducing SAC failures and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of semiconductor device is increased, then the memory capacity is improved, but the contact size is reduced and aspect ratio is increased causing SAC fail
Solution Approach 1:
The patent applies preliminary action by forming the buried gate structure before contact formation, and by pre-defining the contact hole pattern using the gate structure as a reference. This preliminary positioning ensures that subsequent contact holes are accurately aligned, preventing SAC fail even as contact sizes are reduced for higher integration.
Solution Approach 2:
The patent uses the buried gate structure and its associated insulating layers as an intermediary reference framework. The gate structure serves as a mediator that defines the spatial relationship between memory cells and guides the formation of contact holes, ensuring precise alignment without requiring additional alignment steps.
2Quantity of substance
If the contact size is reduced for higher integration, then the device density is improved, but the aspect ratio of contact is increased making alignment more difficult
Solution Approach 1:
The patent implements self-service alignment where the contact hole pattern is automatically defined by the existing gate structure and insulating layer configuration. The gate structure serves its dual function as both the device element and the alignment reference, eliminating the need for separate alignment marks or complex multi-step alignment procedures.
Solution Approach 2:
The patent merges the alignment reference function with the gate structure itself. Instead of requiring separate alignment marks or reference patterns, the gate structure and its surrounding insulating layers are combined to serve as the alignment reference, simplifying the overall fabrication process while maintaining precision.
3Reliability
If the buried gate structure is formed to prevent SAC fail, then the landing plug alignment is improved, but the storage electrode contact may fail to connect to active region
Solution Approach 1:
The patent solves the connection problem by extending the contact hole formation process into a deeper dimension. Contact holes are formed to penetrate through multiple insulating layers down to the active region, ensuring connection despite the buried gate structure. This vertical extension into another dimensional space allows the contact to bridge the gap created by the buried gate configuration.
Solution Approach 2:
The patent applies preliminary action by pre-forming the buried gate structure and its insulating layers before contact hole formation. This preliminary configuration establishes the spatial framework that guides subsequent contact hole etching, ensuring that contacts are positioned to reach the active region while avoiding the gate structure.
4Strength
If the insulating layer is formed on buried gate, then the gate structure is protected, but the buried gate may be oxidized
Solution Approach 1:
The patent employs composite material protection by using multiple insulating layers with different properties. The first insulating layer provides primary protection, while the second insulating layer adds an additional barrier against oxidation. This composite structure combines the protective benefits of different materials to comprehensively shield the buried gate from oxidation while maintaining electrical isolation.
Solution Approach 2:
The patent applies beforehand cushioning by forming protective insulating layers on the buried gate structure before exposing it to processes that could cause oxidation. These pre-formed protective layers act as a cushion or barrier that prevents direct contact between the gate structure and oxidizing environments during subsequent fabrication steps.
Data Source
AI summary
A semiconductor and a method for forming the same are disclosed. The method for forming the semiconductor device includes forming a buried gate on a semiconductor substrate including an active region, forming an insulating layer on the semiconductor substrate, selectively removing the insulating layer from at least an upper part of the active region, forming a bit line on an upper part between the buried gates formed on the active region, and forming a storage electrode contact that is formed at both sides of the bit line and has an extended lower part, so that prevents short circuiting between the storage electrode contact and the bit line, and improves contact resistance by enlarging a contact area between the storage electrode contact and the active region, so that unique characteristics of the semiconductor device are improved.