Buried Gate Extended Drain Transistor Reducing Channel Resistance
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Solution Overview
Problem
Conventional extended drain MOS (EDMOS) transistors face limitations in achieving lower resistance and higher current flow without increasing the device area, primarily due to the contribution of channel resistance to overall resistance.
Innovation Solution
A planar extended drain transistor design where the control gate is partially buried into the channel region, creating multiple current paths and reducing channel resistance by increasing the area influenced by the control gate, while maintaining a single drift region between the channel and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drift region is extended and doping is lowered to increase breakdown voltage, then breakdown voltage is improved, but the overall resistance is increased and current flow is limited
Solution Approach 1:
The control gate is extended into a third dimension by burying it partially or fully into the channel region, transforming from a surface-level structure to a multi-level structure. This dimensional change increases the effective gate-channel interaction area without increasing the planar footprint, thereby reducing channel resistance while maintaining the drift region's breakdown voltage characteristics
Solution Approach 2:
The control gate is nested within the channel region, with the gate structure embedded inside the semiconductor layer. This nesting arrangement allows the gate to influence multiple channel paths simultaneously, reducing overall resistance without requiring additional device area or compromising the drift region's high breakdown voltage properties
2Reliability
If the channel region area is increased to reduce channel resistance, then current flow is improved, but the overall device area is increased
Solution Approach 1:
Instead of expanding the channel region in the planar direction (increasing device area), the control gate is extended vertically into the channel region. This dimensional transformation allows the gate to control multiple current paths within the same footprint, reducing channel resistance without increasing device area
Solution Approach 2:
The buried control gate structure serves multiple functions simultaneously: it reduces channel resistance by influencing multiple current paths, maintains a compact device footprint, and preserves the drift region's breakdown voltage characteristics. This multi-functionality resolves the contradiction between reducing resistance and maintaining small area
Data Source
Figure 1A~1B
Figure 2
Figure 3A~3B
AI summary
A planar extended drain transistor (100) is provided which comprises a control gate (102), a drain region (109), a channel region (107), and a drift region (108), wherein the driftregion (108) is arrangedbetween the channel region (107) and the drain region (109). Furthermore, the control gate (102) is at least partially buried into the channel region (107) and the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109).