Buried Gate Structure With FD-SOI Isolation for BCAT Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuit devices with buried channel array transistors (BCATs) experience increased integration and reduced design rules, the narrow line widths of buried word lines lead to electrical coupling and disturbance phenomena, complicating the formation and uniformity of buried channel transistors.
Innovation Solution
The implementation of a fully depleted silicon on insulator (FD-SOI) structure isolates the gate structure from the substrate, and a semiconductor channel structure layer is formed on each buried word line to reduce electrical coupling and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width of buried word lines is reduced to increase integration density, then the integration degree is improved, but electrical coupling and disturbance phenomena occur between adjacent word lines
Solution Approach 1:
The patent divides the continuous substrate into isolated regions by introducing element isolation films between adjacent buried word lines. This segmentation physically separates the electrical fields of neighboring word lines, preventing coupling and disturbance phenomena while maintaining high integration density through close spacing of the isolated structures.
Solution Approach 2:
The element isolation film acts as an intermediary insulating layer positioned between adjacent buried word lines. This intermediate structure blocks electrical field interaction and charge carrier diffusion between neighboring transistors, eliminating coupling effects while allowing the word lines to be placed closer together for higher integration.
2Productivity
If the line width of buried word lines is reduced to increase integration density, then the integration degree is improved, but the formation uniformity of buried channel transistors deteriorates
Solution Approach 1:
By segmenting the substrate with element isolation films, each buried channel transistor is formed in an isolated region with well-defined boundaries. This segmentation provides clear lateral confinement for channel formation, ensuring uniform transistor characteristics even when word line spacing is reduced for high integration.
Solution Approach 2:
The element isolation films create locally distinct regions with different electrical properties. Within each isolated region, the channel formation conditions are uniformly controlled, while adjacent regions are electrically separated. This local quality control ensures consistent transistor performance across the entire device despite reduced overall dimensions.
3Reliability
If element isolation films are introduced to isolate buried word lines, then electrical coupling is reduced, but the device structure complexity increases
Solution Approach 1:
The element isolation films are merged with the existing substrate preparation and transistor formation processes. The isolation structures are formed as an integrated part of the device fabrication sequence, combining multiple functions (isolation, definition of active areas, and mechanical support) into a unified structure rather than adding separate complex components.
Solution Approach 2:
The element isolation films serve multiple functions simultaneously: they provide electrical isolation between adjacent buried word lines, define the lateral boundaries of active areas for channel formation, and provide mechanical support for the thin film structures. This multi-functionality reduces the need for additional specialized structures, maintaining relative simplicity despite enhanced isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high integration, high reliability, and excellent electrical performance by blocking electron and hole movement with the outer insulating layer, reducing electrical disturbances and improving transistor uniformity.
Implementation Method 1
an outer insulating layer conformed along an inner wall of the gate trench... blocking electron and hole movement with the outer insulating layer, reducing electrical disturbances
Data Source
AI summary
An integrated circuit device includes a substrate including an element isolation film defining an active area, and a gate structure buried in the active area of the substrate. The gate structure includes a gate trench, an outer insulating layer conformed along an inner wall of the gate trench, a channel structure layer conformed on the outer insulating layer, a gate insulating layer conformed on the channel structure layer, a gate electrode layer filling a lower area of the gate trench, and a capping insulating layer on the gate electrode layer, the capping insulating layer filling an upper area of the gate trench.