Buried-Gate Structure Using Monocrystalline Silicon to Reduce GIDL

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Solution Overview

Problem

The miniaturization of semiconductor devices leads to increased gate-induced drain leakage (GIDL) in buried-gate transistors, which is exacerbated by the high resistance of polysilicon gates, affecting device performance.

Innovation Solution

The use of a monocrystalline silicon layer instead of metal in the gate of buried-gate transistors reduces GIDL and lowers gate resistance, combined with a metal layer and barrier layers to maintain performance and prevent diffusion issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal gate (tungsten) is used in buried-gate transistors, then wordline resistance is reduced, but gate-induced drain leakage (GIDL) increases significantly

Engineering Contradiction:
Improvewordline resistanceVSAvoidgate-induced drain leakage
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The gate structure uses different materials for different regions: polysilicon or monocrystalline silicon in the region prone to GIDL effect (near the drain) and metal (tungsten) in other regions. This local differentiation allows the gate to have low resistance overall while suppressing GIDL in the critical region where it occurs.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The gate is constructed as a composite structure combining multiple materials (polysilicon, monocrystalline silicon, and metal) with different electrical properties. This composite approach allows the gate to simultaneously achieve low resistance (from metal) and low GIDL effect (from semiconductor materials in the critical region).

Inventive Principle:
Principle #40Composite materials

2Object-generated harmful factors

If polysilicon gate is used to reduce GIDL effect, then GIDL is reduced, but gate resistance increases significantly

Engineering Contradiction:
Improvegate-induced drain leakageVSAvoidgate resistance
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The gate uses polysilicon or monocrystalline silicon only in the specific region where GIDL occurs (near the drain), while using metal in other regions. This localized approach minimizes the GIDL effect without requiring the entire gate to be made of high-resistance polysilicon.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The composite gate structure combines the GIDL-suppressing properties of polysilicon/monocrystalline silicon with the low-resistance properties of metal, achieving both low GIDL and low gate resistance simultaneously through material composition rather than single-material selection.

Inventive Principle:
Principle #40Composite materials

3Productivity

If device size is reduced for miniaturization, then device density increases, but GIDL effect becomes more severe

Engineering Contradiction:
Improvedevice densityVSAvoidgate-induced drain leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

As devices are miniaturized, the gate structure employs localized semiconductor materials (polysilicon or monocrystalline silicon) in the drain-proximal region to specifically counteract the enhanced GIDL effect that occurs in scaled devices, while maintaining overall gate functionality.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The composite gate structure provides a material-based solution to the GIDL problem that intensifies with miniaturization, using the complementary properties of different materials to suppress leakage while maintaining the scaled dimensions required for high device density.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS12040376B2Semiconductor device and preparation method thereof
Publication Date: 2024.07.16 CHANGXIN MEMORY TECH INC
  • US12040376B2 patent drawing
  • US12040376B2 patent drawing
  • US12040376B2 patent drawing

AI summary

A semiconductor device, including: a substrate; a gate oxide layer located in or on the substrate; and a gate located on a surface of the gate oxide layer, the gate including a monocrystalline silicon layer.