Buried Gate Height Differential for GIDL Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in design rule for semiconductor memory devices leads to a short channel effect, increased parasitic capacitance, and exacerbated Gate Induced Drain Leakage (GIDL) in buried word line structures, which deteriorates the refresh characteristic and operation reliability of semiconductor devices.
Innovation Solution
A method for manufacturing semiconductor devices involves forming a buried gate with an operation gate and a non-operation gate, where the height of the non-operation gate is lower than the operation gate, preventing ion-implanted active region overlap and reducing GIDL, thereby improving the refresh characteristic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the design rule is reduced to increase data storage capacity, then the unit cell size is reduced, but the channel length becomes too short causing short channel effect and DIBL
Solution Approach 1:
The patent introduces a vertical dimension to the channel structure by forming a recess in the semiconductor substrate and creating a three-dimensional channel that extends vertically. This allows the channel length to be maintained in the vertical direction even when the horizontal design rule is reduced, thereby preventing short channel effect and DIBL while enabling smaller unit cell footprint.
2Object-affected harmful factors
If a buried word line structure is used to reduce parasitic capacitance, then the electric isolation is improved, but the Gate Induced Drain Leakage characteristic is magnified
Solution Approach 1:
The patent applies different heights to different gate electrode layers: the first gate electrode layer (operation gate) has a first height, while the second gate electrode layer (non-operation gate) has a second height lower than the first. This local quality differentiation allows the non-operation gate to prevent GIDL by reducing overlap with ion-implanted active regions, while the operation gate maintains proper functionality for charge transfer.
Solution Approach 2:
The gate electrode structure is segmented into multiple layers with different heights and functions. The operation gate and non-operation gate are separated vertically, allowing independent optimization of each layer's characteristics to address different functional requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents GIDL and enhances the refresh characteristic of semiconductor devices by maintaining a higher threshold voltage and reducing parasitic capacitance, thus improving the operational reliability.
Implementation Method 1
preventing overlap of the ion-implanted active region with the non-operation gate
Data Source
AI summary
A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.