Buried Source Follower Gate Layout for Low-RTS Image Sensors

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Solution Overview

Problem

Current image sensors face challenges in reducing random telegraph signal (RTS) noise, which affects their performance and image quality.

Innovation Solution

The image sensor design includes a source follower transistor with a buried portion that is closer to the drain region than the source region, and a specific gate structure that enhances the effective channel length, thereby improving RTS noise properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the channel length is increased to reduce RTS noise, then the device area increases, but the pixel size and integration density are reduced

Engineering Contradiction:
ImproveRTS noise propertyVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The gate pattern extends in the vertical direction (depth dimension) by including a buried portion that protrudes below the main body portion. This three-dimensional gate structure increases the effective channel length for RTS noise suppression without proportionally increasing the planar device area, as the noise-reducing functionality is achieved through the vertical extension rather than horizontal expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The buried portion of the gate pattern is nested within or adjacent to the recess region, creating a compact structure where the noise-reducing gate extension is integrated into the existing device footprint. This allows the effective channel length to be increased while maintaining compact spatial arrangement and not significantly increasing the overall device area.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If the gate pattern is extended to increase effective channel length, then the manufacturing complexity increases, but the fabrication process remains manageable

Engineering Contradiction:
ImproveRTS noise propertyVSAvoidgate pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate pattern is segmented into two distinct portions: a main body portion and a buried portion. This segmentation allows each portion to be optimized independently for its specific function while simplifying the overall manufacturing process. The buried portion can be formed using standard semiconductor fabrication techniques such as selective epitaxial growth or deposition in a recess region, making the increased complexity manageable through modular construction.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240178253A1Image sensor
Publication Date: 2024.05.30 SAMSUNG ELECTRONICS CO LTD
  • US20240178253A1 patent drawing
  • US20240178253A1 patent drawing
  • US20240178253A1 patent drawing

AI summary

An image sensor includes a substrate including an active region with source and drain regions, a source follower gate pattern on the active region, the drain and source regions being adjacent to first and second side surfaces of the source follower gate pattern, respectively, and a gate insulating layer between the active region and the source follower gate pattern. An upper portion of the active region includes a recess region, and the source follower gate pattern includes a body portion on the active region and a buried portion provided in the recess region and protruding below the body portion. A distance between the first and second side surfaces is a first length, and a distance between a center of the buried portion and the first side surface is a second length. The second length is greater than or equal to 0.1 times the first length and is less than 0.5 times the first length.