Buried Gate Memory Device Reducing Channel Resistance
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Solution Overview
Problem
As memory devices become more integrated, the short channel effect degrades due to miniaturized patterns, leading to increased channel resistance and reduced transistor characteristics.
Innovation Solution
The memory device design includes a substrate with active and isolation areas, trenches, and gate trenches that cross both, where the isolation layer's width is greater than the active pattern's width, and a gate line stack with a gate insulating layer and capping layer, enhancing the channel length and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase integration density, then the integration degree is improved, but the short channel effect deteriorates and channel resistance increases
Solution Approach 1:
The gate electrode is extended vertically into the substrate to form a buried gate structure. This three-dimensional configuration allows the gate to control the channel from below, effectively increasing the gate control area without increasing the planar footprint, thus maintaining high integration density while improving transistor characteristics
Solution Approach 2:
The buried gate electrode is formed before the channel layer is deposited. This preliminary positioning of the gate structure allows subsequent layers to be formed around it, creating an effective buried gate configuration that reduces short channel effects while maintaining compact device dimensions
2Reliability
If the gate trench width in isolation layer is increased, then the gate line contact area is improved, but the device complexity increases
Solution Approach 1:
The gate trench width is made non-uniform, being wider in the isolation layer region and narrower in the active pattern region. This local variation optimizes the gate line contact area in isolation regions to reduce resistance, while maintaining appropriate dimensions in active regions to avoid excessive complexity
Solution Approach 2:
The gate trench structure serves multiple functions: it provides electrical connection for the gate line in isolation regions, defines the channel region in active areas, and controls the buried gate depth. This multi-functionality reduces the need for separate structures, thereby reducing overall device complexity
Data Source
AI summary
A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern.