Buried Gate Segmentation for GIDL Reduction in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, variations in the etchback depth during the fabrication of buried gates lead to gate-induced drain leakage (GIDL), reducing cell retention time and deteriorating device characteristics due to overlap between junction regions and gate metal.
Innovation Solution
A semiconductor device design featuring a first and second buried gate with distinct metal contacts and voltage control, where the second buried gate overlaps with an ion implantation region, and is floated when the first buried gate is turned off to prevent GIDL, while applying different voltages based on the turn-on or turn-off state to manage channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single buried gate is used to reduce channel resistance, then channel resistance is reduced, but gate-induced drain leakage occurs due to overlap with ion implantation region
Solution Approach 1:
The single buried gate is divided into two separate buried gates: a first buried gate positioned to reduce channel resistance, and a second buried gate positioned to overlap with the ion implantation region. This segmentation allows each gate to perform its specific function independently, preventing GIDL while maintaining low channel resistance.
Solution Approach 2:
A voltage control unit is introduced as an intermediary component to independently control the potentials of the first and second buried gates. This mediator enables precise voltage management, applying appropriate potentials to each gate to prevent harmful interactions while optimizing device performance.
2Ease of manufacture
If etchback depth is varied during fabrication, then manufacturing flexibility is improved, but junction region and gate metal overlap occurs reducing cell retention time
Solution Approach 1:
The gate structure is segmented into multiple buried gates with distinct functions. The first buried gate handles channel conduction while the second buried gate manages the interface with the ion implantation region. This segmentation decouples the functions, allowing manufacturing variations in etchback depth without causing harmful overlaps that would reduce cell retention time.
Solution Approach 2:
Different regions of the gate structure are assigned different qualities and functions. The first buried gate region is optimized for channel resistance reduction, while the second buried gate region is positioned to prevent overlap with the ion implantation region. This local differentiation ensures that manufacturing variations do not uniformly affect the entire gate structure.
3Adaptability or versatility
If buried gate is extended to pad region, then device integration is improved, but gate induced drain leakage occurs when junction and gate overlap
Solution Approach 1:
The extended gate structure is divided into multiple buried gates positioned at different locations. The first buried gate extends toward the pad region for integration purposes, while the second buried gate is strategically positioned to prevent overlap with the ion implantation region. This segmentation maintains the benefits of extended gate integration while avoiding harmful GIDL effects.
Solution Approach 2:
Different segments of the extended gate structure are assigned different functional qualities. The first buried gate segment provides integration connectivity to the pad region, while the second buried gate segment is configured to prevent overlap with charged regions. This local quality differentiation enables both high integration and prevention of GIDL.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate with a cell region, a second pad region, and a first pad region between the second pad region and the cell region, a first buried gate buried in a trench of the semiconductor substrate, and extended from the cell region to the second pad region, and a second buried gate buried in the trench of the semiconductor substrate, disposed over and spaced apart from an upper part of the first buried gate, and extended from the cell region to the first pad region.