Buried Gate Memory Structure with Surrounding Contacts
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Solution Overview
Problem
The increasing demand for larger capacity semiconductor devices is hindered by the limitation in reducing chip size, leading to increased contact resistance in storage node contacts and bit line contacts, which degrades electrical characteristics.
Innovation Solution
A semiconductor device structure featuring active regions defined by an isolation layer, a buried gate in a gate trench, and storage node contacts surrounding three sidewalls of a junction region, with multiple active regions sharing a buried gate and arranged in parallel, to reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip size is increased to integrate more memory cells, then the number of memory cells per wafer is reduced, but device fabrication productivity is reduced
Solution Approach 1:
The patent divides the memory cell structure into multiple active regions (first, second, third, and fourth active regions) that share common gates and contacts. This segmentation allows for more compact cell layout by reducing the area required per individual memory cell, thereby increasing the number of cells that can be integrated on a single wafer without compromising fabrication productivity.
Solution Approach 2:
The patent merges multiple memory cell components by implementing shared gates (first gate, second gate, third gate, fourth gate) that control multiple active regions simultaneously. This merging reduces the overall cell area by eliminating redundant structures, allowing higher cell density per wafer while maintaining efficient fabrication processes.
2Quantity of substance
If areas of storage node contacts and bit line contacts are reduced to increase integration, then contact resistance is increased, but electrical characteristics are degraded
Solution Approach 1:
The patent transitions from conventional planar contacts to three-dimensional contacts that surround three sidewalls of the first junction region. This dimensional change increases the contact area and reduces contact resistance by utilizing vertical sidewall surfaces, thereby improving electrical characteristics while maintaining high integration density.
Solution Approach 2:
The storage node contact is designed to surround three sidewalls of the first junction region, creating a nested structure where the contact envelops the junction region. This nested configuration maximizes the contact area with the junction region, reducing contact resistance and improving electrical characteristics without increasing the planar footprint of the device.
Data Source
AI summary
A semiconductor device including a storage node contact that surrounds three sidewalls of an active region to increase the contact area between the storage node contact and the active region is provided.