Buried Gate Sub-Word Line Drivers for Reliable Transistor Channels
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Solution Overview
Problem
As semiconductor devices shrink in size, the reduced length of gate channels in the peripheral circuit region leads to deteriorating transistor characteristics, particularly in the sub-word line driver region.
Innovation Solution
The semiconductor device incorporates a buried gate structure for transistors in the sub-word line driver region, which secures the gate channel length and integrates with the cell region's word lines, using a shared mask process to simplify fabrication and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of semiconductor devices is reduced, then device integration is improved, but the length of gate channel in peripheral circuit region deteriorates
Solution Approach 1:
The patent applies buried gate structures that extend vertically into the substrate rather than only horizontally, utilizing the vertical dimension to achieve longer effective gate channel lengths without increasing the planar device footprint. This allows the gate channel to reach deeper into the substrate, compensating for the reduced lateral dimensions.
Solution Approach 2:
The buried gate structure is nested within the substrate, with the gate electrode embedded in a trench that extends into the substrate. This nesting approach allows the gate structure to occupy vertical space within the existing device footprint, effectively increasing channel length without proportionally increasing device area.
2Reliability
If gate channel length is increased, then transistor characteristics are improved, but device integration is worsened
Solution Approach 1:
By transitioning from planar gate structures to vertically embedded buried gates, the patent achieves longer channel lengths through vertical extension into the substrate. This dimensional transition allows improved transistor characteristics while maintaining compact lateral device dimensions.
Solution Approach 2:
The buried gate structure is applied selectively to transistors in the sub-word line driver region where longer channel length is most critical for maintaining transistor characteristics. This localized application optimizes performance in the most demanding circuit regions without requiring increased device area throughout the entire semiconductor device.
3Manufacturing precision
If separate mask processes are used for cell region and sub-word line driver region, then manufacturing precision is improved, but fabrication complexity is worsened
Solution Approach 1:
The patent employs a unified mask pattern that serves dual purposes: defining the gate structure for cell region transistors and simultaneously defining the buried gate structure for sub-word line driver transistors. This multi-functional mask approach eliminates the need for separate mask processes, reducing fabrication complexity while maintaining precision through a single patterning step.
Solution Approach 2:
The patent merges the mask processes for cell region and sub-word line driver region into a single process step. By combining these previously separate operations into one unified mask application, the patent reduces the number of fabrication steps and simplifies the overall manufacturing process while achieving the desired structural differentiation through subsequent selective etching or deposition.
Data Source
AI summary
A semiconductor device includes a substrate; and a plurality of sub-word line drivers, each of the sub-word line drivers including a plurality of transistors, wherein at least one of the plurality of transistors has a buried gate structure positioned in the substrate.