Buried Interconnect Layout for Low-Resistance BPR Connections
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Solution Overview
Problem
Conventional methods for forming buried power rails (BPRs) in integrated circuits face challenges in achieving low resistance connections with improved reliability and process margins, due to increased sensitivity to stochastic errors and overlay issues in the integration process.
Innovation Solution
A method is developed to form a buried interconnect structure by creating a trench in the isolation layer, lining it with a dielectric layer, and selectively etching contact openings to form local interconnects that extend laterally, ensuring a low resistance connection with self-aligned via interfaces and maintaining isolation margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PV and local interconnect are enlarged along the critical dimension to reduce resistance, then the contact interface area increases, but the spacing between adjacent interconnects decreases, reducing process margins and increasing sensitivity to overlay errors
Solution Approach 1:
The patent transitions from enlarging interconnects in the critical dimension (planar dimension) to extending them in the lateral dimension parallel to the substrate. The via-to-BPR connection is enlarged laterally along the substrate surface rather than increasing the vertical or critical dimension, thereby reducing resistance without compromising spacing margins in the critical dimension.
Solution Approach 2:
Instead of enlarging the via and local interconnect in the vertical/critical dimension to reduce resistance, the patent inverts the approach by enlarging them in the lateral dimension parallel to the substrate. This reversal of the enlargement direction resolves the contradiction between reducing resistance and maintaining process margins.
2Reliability
If the PV contact interface is enlarged to reduce resistance, then the contact area between PV and BPR increases, but the process margins for PV formation are reduced
Solution Approach 1:
The patent changes the dimension of enlargement from the vertical/critical dimension to the lateral dimension parallel to the substrate. The via-to-BPR connection is extended laterally, increasing contact area and reliability without increasing complexity in the critical dimension, thereby maintaining simpler formation processes with adequate margins.
3Reliability
If the local interconnect width is increased to reduce resistance, then the contact interface area increases, but the spacing between laterally adjacent interconnects decreases
Solution Approach 1:
The patent extends the local interconnect in the lateral dimension parallel to the substrate rather than increasing its width in the critical dimension. This lateral extension increases the contact interface area and reliability while maintaining adequate spacing between adjacent interconnects, as the extension occurs in a different dimensional direction.
Data Source
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AI summary
There is provided a method for forming a semiconductor device, comprising: forming a trench for a buried interconnect structure between a first and second fin structure; lining the trench with a dielectric layer; etching a contact opening in a first portion of the dielectric layer adjacent a first region of the first fin structure, while masking the second portion of the dielectric layer adjacent a second region of the second fin structure directly opposite the first region; forming a local interconnect trench, the local interconnect trench extending between the first and second regions, wherein the second portion of the dielectric layer partitions the local interconnect trench into first and second trench portions; and forming first and second local interconnects in the first and second trench portions, wherein the first and second local interconnects are separated by the second portion of the dielectric layer.